ISSCC2018 (3)

February 15th, 2018

Yoshioka (Toshiba) presented a 20 channel TDC/ADC Hybrid SoC with 200m ranging LiDAR.  The goal of this work was to develop a LiDAR system that can work for short distances (urban driving situations) as well as for larger distances, up to 200m (high-way situations, but not for Germany, there you need even larger distances !).  The complete system relies on a “Smart Accumulation Technique” which was explained during the presentation, but which is too complicated to explain here in a few words.  The advantage of this SAT method is the combination of working at longer distances while maintaining image quality.  Special attention was given to the choice of the LiDAR quantizer circuitry.  A TDC is fast and consumes a small area, but acquires only the ToF info, while an ADC is compatible with the proposed SAT method, but overall a ADC is slow and consumes a large area.  But if it is difficult to make a choice, then implement both !  And that is what is done in this hybrid concept : the TDC is used for short distances (0 … 20 m), the ADC is used for larger distances (20 … 200 m).

 

Bamji (Microsoft) presented a kind of follow-on of the work presented a few years at ISSCC and very well described in JSSC (they got the Walter Kosonocky Award for this publication).  A 1 Mpixel ToF image sensor showed impressive results : 3.5 um pixels, GS, 320 MHz demodulation, modulation contrast at 320 MHz is 78 %, QE of 44 % at 860 nm, and with a per-pixel AGC to obtain HDR.  The device is realized in 65 nm BSI (1P8M) process.  Unfortunately it was not explained (even not in Q&A) how the GS with an efficiency of 99.8 % is realized.

 

Ximenes (TU Delft) presented a 256×256 SPAD based ToF sensor.  The device is made in 45 nm (then you should be able to guess who fabricated the chip) and is stacked on a 65 nm logic chip.  It was claimed that for the very first time the digital supporting part of the detector was fully digitally synthesized.  Pixel pitch is 19.8 um with a fill factor of 31.3 %.  The overall system allows a distance range of 150 … 430 m with a precision in the order of 0.1 % and an accuracy of around 0.3 %.

 

Gasparini (FDK) closed the session with a talk about a 32×32 pixel array for quantum physics applications.  The presenter tried to explain the concept of entangled photons, but I am not sure whether all people in the audience understood this concept after a full day of presentations.  The sensor is based on SPADs, each with its own quenching circuit and TDC.  The chip was realized in a low-cost 150 nm 1P6M CMOS standard technology, pixel size 44.64 um (with in-pixel time-stamping, not surprising if David Stoppa is one of the co-authors) and almost 20 % fill-factor.  Implemented are features to skip rows and frames to speed the overall imaging system.

 

Overall the imaging session of the ISSCC2018 was one of high quality, very well prepared presentations, great sheets (16:9 for the first time at ISSCC).  There was a large audience (the largest ever for the image sensor session at this conference), and during the Q&A long waiting lines were piling up in front of the microphone.

Take away message : everything goes faster, lower supply voltages, lower power consumption, stacking is becoming the key technology, and apparently, the end of the developments in our field is not yet near !  The future looks bright for the imaging engineers !!!

Albert, 15-02-2018.

ISSCC2018 (2)

February 14th, 2018

Kumagai (Sony) talked about about a 3.9 MPixel Event-Driven BSI stacked CIS.  It is not the kind of sensor that is being researched by the group of Tobi Delbruck, neither what is being done at Chronocam.  But in this new device, the data is reduced drastically by on-chip binning, column wise as well as row wise.  The overall resolution of 3.9 Mpixels is reduced to on 16×5 macro pixels.  In this “macro” pixel mode, the power consumption is drastically reduced as well, and the sensor behaves in a sort of sleeping mode.  Once the sensor detects any motion in the image (by means of frame differencing), the device wakes up and switches to the full resolution mode.  Also in the full resolution mode, the CIS works at 1.8 V supply voltage.  So that keeps the power consumption low, also in full resolution.  The device is realized in 90 nm 4CU CIS technology, on top of a 40 nm 1Al6Cu logic chip.  Pixels are 1.5 um x 1.5 um.  In full resolution, 60 fps, 10 bits, the device consumes 95 mW.  In sensing 16×5 macro pixel mode, the power is lowered to 1.1 mW at 8 bits and 10 fps.  Random noise is 1.8 e, resulting in a dynamic range of 67 dB at 10 bits and full resolution, and of 96 dB in the sensing 16 x 5 mode.

 

Chou (TSMC) explained the ins and outs of a 1.1 um CIS 13.5 Mpixel, 34 fps with switching options to 514 fps at 720p, 230 fps at 1080p and 58fps at 2160p.  The basic idea is to skip columns in the reduced resolution modes, while still using the full bank of column-level ADCs.  In this way 2 or 3 rows can be read out at the same time which increases the frame rate.  Because the different options to connect the columns to the ADCs, the interconnect is a bit complex, but of course the design and lay-out of the device has to be done only once.  Some numbers : technology used for the sensor is 45 nm 1P4M, for the logic 65 nm 1P5M.  Noise is 1.8 e, column FPN 0.28 e, full well 4458 e, resulting in a dynamic range of 67.5 dB.

Yasue (NHK) presented a new 8K4K device for ultra-HD broadcasting applications.  Needs to be ready to provide us with super quality slow motion pictures of Tokyo 2020 !  The sensor runs in a progressive mode.  Key characteristics are low noise (for that reason a 3-stage pipeline ADC is used), duplicated source followers with parallel operation (to speed up the device) and an ultimate speed of 480 fps (to realize the super slomo option).  The pipeline ADC consists of a folding integration stage, a cyclic stage and a SAR stage.  In 120 fps mode, the ADC works at 14 bits (noise is 3.2 e, 12.5 W), in 240 fps mode, the ADC works in 12 bits (noise is 4.3 e, 9.8 W)  and finally in the 480 fps mode, the ADC works in 10 bits (noise is 24 e, 9 W).  Apparently the specs are almost met in the 120 fps mode (target was 3 e of noise), but there seems to be room to improve at 480 fps.  Maybe next year’s ISSCC ?

 

Albert, 14-02-2018.

ISSCC 2018 (1)

February 13th, 2018

Sakakibara (Sony) presented a paper about a BSI-GS CMOS imager with pixel-parallel 14b ADC.  One can make a global shutter in a CMOS sensor in the charge domain, in the voltage domain, but also in the digital domain.  The latter requires an ADC per pixel (also known as DPS : digital pixel sensor).  And this paper describes such a solution : a stacked image sensor with per pixel a single ADC.  Based on the recent history of Sony technology, it could be expected that this technology was coming.  The ADC (per pixel !) is a single slope ADC with a comparator and a latch per pixel.  The design of the pixel is such that the source follower is already part of the comparator.  That makes the structure very compact, but requires two Cu-Cu contacts between top and bottom layer per pixel.  To get rid of all the data generated by all these ADCs, a pretty complex data line structure is implemented.  The technologies used : 90 nm 1P4M for the top layer, 65 nm 1P7M for the bottom layer.  Pixel size is 6.9 um x 6.9 um, 1.46 Mpixels, noise level 5.15 e in a high power mode of 746 mW @ 660 fps or 8.77 e in a low power mode of 654 mW @ 660 fps.  Dynamic range for the two modes is respectively 70.2 dB and 65.7 dB.  PLS for this global shutter is -75 dB.

 

Nishimura of Panasonic talked about the organic-photoconductive film GS CIS with an in-pixel noise canceller.  It is not the first time that this technology is presented at ISSCC, but this time an extra noise cancellation “trick”  is applied in the pixel to lower the noise.  Do not forget that this pixel is basically a 3T pixel that suffers from kTC noise.  A similar noise cancellation method was applied as what we have seen earlier with the so-called “active reset”, but no longer on column level, this time on pixel level. Key advantage of this device is the GS mode with very good PLS (- 110 dB), tunable sensitivity by biasing the right voltage across the photoconductor, very high saturation level.  The paper claims that the reset noise is lowered by a factor of 10, while the saturation level is increased by a factor of 10 (but the high saturation mode cannot be combined with the low noise level).  The pixel size is 3 um x 3 um, for a 8192 x 4320 pixels, 60 fps, 12 bit ADC, 65 nm process technology 1P4Cu1Al, noise of 8.6 e (in the proceedings, not consistent with the presentation where it was mentioned 4.5 e).  But again not a single indication about dark current and dark non-uniformities.  During the presentation as well as after the session, super quality images were shown, but all was prerecorded.

 

Choi of Samsung presented 24 Mpixel CIS with a pixel size of 0.9 um, using full-depth deep-trench isolation.  As can be expected, a 0.9 um pixel will suffer from full-well limitations, crosstalk and sensitivity issues.  Unless, a thickness silicon layer (40 % thicker, going from 3 um to 4.25 um, these last numbers are guesses !) is used (for this BSI device) in combination with DTI that goes all the way through the silicon.  So basically you create an isolated island for every single pixel (in the talk it was mentioned that if the pixels are fully isolated from each other by the DTIs, they can be operated at a lower voltage, which is in its turn beneficial for dark current and dark non-uniformities).  The sensor is using stacking with TSVs, and apparently the trenches are filled (with poly-Si ? not sure about this) and are biased with a negative voltage to keep the dark current low.  All techniques mentioned are not new, but their combination for a 0.9 um is new.  The author made a comparison between this new 0.9 um pixel and an existing 1.0 um pixel, and the new one beats the old pixel is all aspects : full well 6000 e, dark temporal noise 1.4 e, dynamic range 64.9 dB, dark current (60 deg.C) 2 e/s.  A strong reduction in white spots and RTS pixels is mentioned in the overview table, but it is not clear what is exactly done in the technology to come to these levels.

 

Albert, 13-02-2018.

Looking for a PhD student and for a postdoc researcher

January 2nd, 2018

In support of my research group at the Delft University of Technology, I am eagerly seeking for a PhD student (4 years) as well as a postdoc researcher (3 years).  Both persons will be working on CMOS image sensors characterized by ultra-low noise and ultra-high speed.

At this moment the CIS research group at the Delft University of Technology is composed out of 4 PhD students and one postdoc researcher.  But recently a new project is granted and this will allow us to expand the group by two more people.  The job of the two additional people will focus on design, lay-out and evaluation of the CMOS image sensors with the aforementioned characteristics.  The expected background of the candidates is electronic engineering.  Starting date : a.s.a.p.

If you are interested, please send you recent CV to A (dot) J (dot) P (dot) Theuwissen (at) tudelft (dot) nl

(I hope it is clear what is meant here, if I correctly spell the e-mail address I will get tons of SPAM).

Albert, 2-1-2018.

 

Good Bye 2017 ! 

December 15th, 2017

Again another year (almost) has passed by.  And then it is a good moment to take a look back of what happened in 2017.

In the beginning of the year Harvest Imaging announced a project in which the reproducibility, variability and reliability of CMOS imagers will be characterized.  The promise was to deliver a first report in the Summer 2017, but the actual amount of measurement work was a bit underestimated and it took a lot of time to perform all the characterization of the cameras.  New hardware and software had to be installed and as you probably know, these kind of things always take more time than expected.  But early September the first report was published and sent to the customers.  The first feedback of the people who acquired the reports was very encouraging.  More reports will follow in the summers of the coming 4 years.  In the meantime also a dedicated program is started to look for the reliability of the cameras when they are stored at 85oC and 85% relative humidity.

On the more scientific level we had the International Image Sensor Workshop 2017 in Hiroshima (Japan).  The meeting was again a highlight w.r.t. organization and information content.  In 4 days about 100 papers/posters were presented.  And I think that all participants went home with a happy face.  Not only a lot of high-quality information could be absorbed, but as usually it was great to meet our imaging peers from the academia and the industrial world.  During the IISS-Board meeting, the undersigned was elected as the president of the International Image Sensor Society for the coming 4 years.

The core business of Harvest Imaging is of course the training and courses conducted in the field of digital imaging.  And in 2017 two milestones were reached : course number 200 was organized in Delft.  And of all these courses, 100 of them were organized by CEI.  This “century” milestone was celebrated in Barcelona.  I would like to take the opportunity to thank again all participants who ever attended one or more of my trainings.  Without participants there would be no courses or trainings !!

Finally something about the yearly Harvest Imaging Forum : this year Christian Enz (EPFL) entertained us in the field of “Low Noise for Analog Devices and Circuits”.  Great speaker, and a subject that was, is and will remain a hot topic.  In all my consulting activities I never ever had a customer with the complain : “the noise of my sensor is too low”, it remains the challenge to make today’s noise lower than yesterday’s.

New in 2017 was the start of the Harvest Imaging Newsletter.  Communication to the outside world about the “products” of Harvest Imaging stays crucial.  Very often I do think that the imaging world knows what Harvest Imaging is doing and is not doing, but it happens regularly that people still come with questions about the activities of Harvest Imaging.  So it is a matter of informing and informing my customers again and again about what is when and where available.

So 2017 is almost completed, and then the question is : “What will bring 2018 ?”.  Well I think it will be more of the same.  Although there will be no IISW in 2018, the next one will take place in 2019 somewhere in the USA.  But the trainings/courses will continue (many in-house and open courses are already booked), consulting will continue as well as the work on the reproducibility, variability and reliability project.  Although, it is expected that in 2018 CEI will come with a new product based on my courses.  For sure, I will keep you informed once this new product comes on the market.  Stay tuned !!

Wishing all my readers a Merry Christmas and a Happy New Year.  “See” you soon.

Albert, 12-12-2017.

Harvest Imaging Forum 2017

November 25th, 2017

Together with the speaker/presentater/instructor Christian Enz (EPFL), the final agenda for the Harvest Imaging Forum 2017 on “Noise in Analog Devices and Circuits” is defined.  I am happy to share it with you :

9:00 – 9:15 Introduction to the forum
9:15 – 10:45 Introduction, Random signals and noise, Main noise sources of circuit components, Noise models of basic components
10:45 – 11:15 Break
11:15 – 12:45 Noise Calculations in Circuits, Noise calculation in continuous-time (CT) circuits, Noise sampling
12:45 – 14:00 Lunch break
14:00 – 15:30 Noise calculation in switched-capacitor (SC) circuits, Noise simulation
15:30 – 16:00 Break
16:00 – 17:30 Trade-offs between Noise and Power Consumption, The simplified EKV MOS transistor model
19:00 – 20:30 Dinner
9:00 – 10:30 The simplified EKV MOS transistor model, The concept of inversion coefficient and the  design methodology, Basic trade-offs in analog design
10:30 – 11:00 Break
11:00 – 12:30 Figures-of-merit (FoMs) as design guidelines, Key FoMs parameters extraction
12:30 – 13:45 Lunch break
13:45 – 15:15 Noise and Offset Reduction Techniques, Switch nonidealities, The Autozero (AZ) technique, The Chopper Stabilization (CS) technique, Recent trends in noise and offset reduction techniques
15:15 – 15:45 Break
15:45 – 17:15 Example of a Low-noise CMOS Imager, CMOS image sensors (CIS), Noise reduction in CIS, A sub 0.5erms noise VGA imager in standard CMOS, Future improvements
17:15 – 17:30 Closure of the forum

Looks more than appealing !!

All further info about the Harvest Imaging Forum 2017 can be found here.

Albert, 25-11-2017.

Reliability of CIS

September 25th, 2017

This morning, Sept. 25th at 11:30am the first set of CIS devices were stored at 85 deg.C/85% humidity to perform a very first reliability test.  I have no idea what is going to happen to the devices, but my intention is to tease those sensors till they finally will break.  At regular times the devices will be taken out of the climate chamber to fully test their characteristics.

All customers who bought the report “Reproducibility, Variability and Reliability of CMOS Image Sensors” will get automatically get the report on these extra tests.

Albert, 25-09-2017.

5th Harvest Imaging Forum : AGENDA update

September 21st, 2017

There is a tiny small update on the agenda of the 5th Harvest Imaging Forum.  One item is added.

Albert, 21-09-2017.

5th Harvest Imaging Forum on NOISE

September 16th, 2017

The 5th Harvest Imaging forum is scheduled for December 2017.  Two sessions were planned, namely on 7/8 Dec. and 11/12 Dec.  2017.  Both sessions will take place !!

I would like to bring to your attention that there will be NO 3rd session for the 2017 forum.  If you still are interested to register, please hurry up before the forum is sold out.

All info about the forum can be found here.

Albert, 16-09-2017.

40 YEAR AGO (2)

September 13th, 2017

 

Actually I am a bit too late to mention that exactly 40 years ago I got my MSc degree from the University of Leuven (Belgium).  As I already indicated in my blog of last year, in 1976 I started to work on my MSc thesis project, and the project finished mid-1977.  The topic of the MSc thesis project was the development of the hardware to drive and read a 256-pixel CCD line sensor.  An object was attached to a small rotating drum and was scanned by means of the CCD line array.  I learned a lot from this practical work, actually not surprising : if you do not know anything of a particular subject, everything you do is new and you constantly learn.

Once I obtained my MSc degree in July 1977, I got the opportunity to stay on-board of the CCD-group and to start a PhD project.  At that time to get funding for their projects, the PhD candidates had to go through a tough oral examination in front of a jury mainly composed out of professors of other (competing) universities.  To prepare myself for this examination, I started working in the CCD-group, headed by prof. Gilbert Declerck. I was involved, in support of another PhD candidate, in the research on the quality of silicon substrates to lower the dark current of the CCDs.  Cor Claeys was my coach during 3 months and he guided me through the clean room.  In this way I got familiar with the silicon processing in general and with the CCD process in particular.  I have seen thousands of silicon defects through the microscope, measured their length and counted the amount of dislocations, stacking faults and other beautiful artifacts.  I got familiar with Wright etch and Secco etch, as well with all kind of annealing steps.  But apparently it was the right preparation for the PhD examination because I could pass the examination, got the funding and could start my own PhD project : the implementation of Indium-Tin-Oxide transparent gate electrodes in the CCD process.  At that time the CCD pixels were based on MOS capacitors with a poly-Si gate electrode.  But the poly-Si did (and still does) absorb part of the incoming light.  To increase the light sensitivity of the pixels, the plan was to replace the poly-Si by a transparent conductive material, such as ITO.  Who could help me with this ?  Actually nobody in our department had any experience with this material and nobody in our department had any experience with the sputtering technique to deposit this material.  Enough challenges ahead for a more-than-interesting CCD-technology project !  The start of a new chapter in my life.

 

Albert, 13-09-2017.