Harvest Imaging Forum 2016 : Update

October 25th, 2016

The Harvest Imaging Forum 2016 is almost sold out : there are only 4 seats left in the session of December 8th and 9th 2016.  In contradiction to the Forum 2015, there will be no extra session organized in coming January !  First come, first served !

Albert, 25-10-2016.

Training Last Week in Dresden (Germany)

October 17th, 2016

Last week I taught the 5-days class “Digital Imaging” organized by CEI.  This time the training took place in Dresden (Germany).  For the very first time we added a company visit to the training (after teaching hours).  We had the luxury to be invited by Aspect Systems to visit their premises in Dresden.  After the course on day3, taxis were organized by CEI to bring the participants to Aspect Systems.  We were welcomed by Marcus Verhoeven, one of the company’s founders.  Marcus explained and showed us the activities of Aspect Systems.  In the imaging community, Aspect Systems is known for their test services, but actually they do much more than that.  Aspect Systems is developing hardware, software, algorithms, optics, mechanics for imaging applications, independent of the final application of the systems (can be testing, evaluation, or other purposes).

We limited the visit to 1 hour, not to overload the course participants too much with technical information after already 3 days of training.  But afterwards that limitation seemed to be a mistake.  Everybody was so enthousiast about the visit and the contact with the real imaging world, that the only complain we got was that the length of the visit : too short.

With this blog, I want to thank Marcus Verhoeven and his co-workers for their time and hospitality to have us at their premises.  Hopefully we can repeat this company-visit experiment when we are again in Dresden for another training.  But then for sure, we spend some more time at Aspect Systems.

Thanks Marcus and team, success with your business !

Albert, 17-10-2016.

Harvest Imaging Forum 2016

October 13th, 2016

For those of you who are still interested in the Harvest Imaging Forum 2016 : there are only 6 seats left in the session of December 8th and 9th 2016, before the forum is sold out.  In contradiction to the Forum 2015, there will be no extra session organized in coming January !  First come, first served !

Albert, 13-10-2016.

AutoSens 2016 in Brussels

September 22nd, 2016

Yesterday morning (Sep. 21st, 2016) I attended a few sessions of AutoSens 2016 in Brussels.  It is a new conference organized by the people who started and grew Image Sensors Auto at the time they were still working for Smithers.  AutoSens was very well attended and was very well organized in a great setting, namely in the Auto-Museum in Brussels.  Excellent choice !

In the morning sessions, there were 3 papers related to image sensors.  Pierre Cambou (YOLE Development) talked about new developments in mobile and their spin-off to automotive applications, Daniel van Nieuwenhove (Softkinetic) gave a nice overview of 3D imaging technologies and how the Softkinetic’s solutions fit into this landscape, and Tarek Lule’s (ST) presentation was about a HDR flicker-free CMOS image sensor.  The latter one had the most technical information, although Tarek did not give any details about the pixel architecture.  But what I understood from his talk is the following : the pixels are making use of multiple photodiodes :

  • a large photodiode is capturing information in an continuous mode during the exposure time, with a high sensitivity and is basically “looking” after details in the darkest parts of the image,
  • a small photodiode that is capturing information in a chopped mode : during the exposure time the photodiode is active during short periods of time and is inactive during the remaining time of the chopping period, it sums the signals obtained during these short periods of time.  In this way, information is collected AT THE SAME TIME as the large photodiode, but because of the size and of the chopping, the diode “looks” after details in the mid-range of the image, motion artefacts can be avoided,
  • a small photodiode that is capturing information in a chopped mode : during the exposure time the photodiode is active during VERY short periods of time and is inactive during most of the time of the chopping period, and it sums the signals obtained during these very short periods of time.  In this way, information is collected AT THE SAME TIME as the large photodiode, but because of the size and the chopping, the diode “looks” after details in the high-range of the image, motion artefacts can be avoided.  The chopping frequencies for the two smaller diodes is the same, the only difference is the duty cycle of active and non-active.

Apparently the pixel needs three photodiodes, but because of the chopping, the work that needs to be done by the two smaller photodiodes can be done by a single one in combination with an appropriate time-multiplexing between the short and very short active times within the chopping period.  So, the pixel is based on two photodiodes in combination with a few storage nodes.  More information was not revealed …

Conclusion : clever idea to make a flicker-free imager with a high-dynamic range (quoted 145 dB).  Not many performance numbers were given, but the overall working of the device was shown by means of a video.  Looking forward to learn more about this device !


Albert, 22-09-2016.


September 22nd, 2016

Most probably several readers of this blog were not yet born in September 1976, but exactly 40 years ago I started my career in solid-state imaging.  Of course I could never ever have guessed that 40 years later I would be still involved in the same discipline.

When I was facing the start of my last year of the MSc-EE studies (at the Catholic University of Leuven, Belgium) in September 1976, I had to choose a MSc thesis subject.  Purely by coincidence I found an MSc thesis project in the team of Gilbert Declerck and under the daily guidance of Jan van der Spiegel, being a PhD candidate in the CCD group.  The topic was based on the development of the hardware around a bi-linear CCD of 256 elements.  The digital driving pulses as well as the analog signal processing needed to be designed and needed to be built on a breadboard.  The CCD needed to be synchronized to a rotating drum, just to show the principle and capabilities of the imaging device.  At that moment, 40 years ago, a bi-linear device of 256 elements was already something special.

I remember that another PhD candidate, being Peter Schreurs, explained to me the basic principles of a CCD.  I still can recall in which lab space it was.  It was Jan van der Spiegel who explained to me the technology of the CCDs and showed me how he made the design and lay-out of the devices.  At that time, CCD image sensors were designed and fabricated in the clean room of the ESAT laboratory (Electonics, Systems, Automation, Technology).  The environment and the atmosphere in the basement of the EE-building was a great stimulation in the learning process in the field of the “young” semiconductor technology.  During the 9 months of the MSc thesis project, and especially for the hardware part of the task, I worked very closely together with Tony van Nuland.  He thought me the practical ins and outs of digital and analog circuitry.  Afterwards seen, this was the very basic start of a long and lasting career in solid-state imaging.

Gilbert Declerck, the promotor of my MSc thesis, became later the CEO of IMEC; Jan van der Spiegel, my daily supervisor became professor at Penn State University in Philadephia (USA); Peter Schreurs who explained to me the working principles of CCDs started a career at Agfa and Tony van Nuland who helped me with the hardware became a specialist in the field of ion implantation and focused-ion beam techniques at the university’s ESAT laboratory.  As you can judge, I was in good company !  Thanks to all of you !


Albert, 22-09-2016.


August 9th, 2016

The stitching story started in the previous blog is not yet complete.  Further explanation deals with one-dimensional versus two-dimensional stitching, and single reticle versus multiple reticle stitching.

The difference between one-dimensional and two-dimensional stitching is straight forward.  If the stitching is done in one direction (vertical OR horizontal), it is known as one-dimensional stitching, if the stitching is done in two directions (vertical AND horizontal), it is known as two-dimensional stitching.  It should be clear that two-dimensional stitching gives the designer much more freedom in his/her design task, and does allow any device size to be designed.  Most of today’s lithographic equipment is capable of handling two-dimensional stitching, but in the earlier days, some type of alignment machines did allow only one-dimensional stitching.  For image sensors, the very first one-dimensional stitching was done by E2V, while the very first two-dimensional stitching was realized by Philips Research Labs.

Another important discussion is the restriction to single reticle stitching or the option for multiple reticle stitching.  If the field of view of the lithographic machine is limited, it should be clear that (to limit the amount of stitchlines in the active imaging area) the full reticle size should be devoted to an array of pixels.  Consequently all peripheral parts and blocks need to be put on a second reticle.  This design strategy is known as multiple reticle stitching.  Unfortunately most fabs are not so happy with multiple reticle stitching because the reticles have to be exchanged during the exposure of the wafers.  This is time consuming, puts a burden on the use of the equipment and is costing a lot of extra money.  For that reason most fabs (if they offer stitching at all) prefer single reticle stitching.  Another important factor to avoid multiple reticle stitching is the cost of the extra mask set.  For more advanced CMOS processes, the mask cost is not negligible anymore compared to the cost of the wafer processing.  It was Philips Research Labs that fabricated for the first time large area imagers based on multiple reticle stitching.

As a consequence, single reticle stitching is much more common than multiple reticle stitching.  In that case, the active imaging array together with the peripheral blocks need to fit on a single reticle size, which leaves a smaller area for the pixel array (compared to a full reticle size in the case of multiple reticle stitching).  Resulting in more exposures for the active area, more stitch lines, more processing time and more expensive processing.  On the other hand, one needs only one mask set.

Altogether in the case of large-area imagers, very often a designer likes to go for multiple reticle, two-dimensional stitching (to avoid too many stitch lines), while most fabs prefer to avoid stitching at all.  It is not always an easy exercise to find an optimum between these two extremes.  There are only a very limited number of fabs/foundries in the world that do allow their customers to go for two-dimensional, multiple reticle stitching.  If stitching is offered at all, then the most common option is single reticle stitching in combination with one-dimensional stitching.

Albert, 09-08-2016.


July 8th, 2016

After the butting, it is now stitching time !

To explain the stitching, Figure 1 is included that shows the complete top-level design/lay-out of an image sensor (CCD or CMOS).


Figure 1 : Sketch of the top-level design of an image sensor.

One can recognize the following parts :

  • The pixel matrix, consisting of r by s pixels,
  • The left (L-) driving and right (R-) driving electronics,
  • Some extra electronics at the top (e.g. biasing circuitry, etc.),
  • The readout part (consisting for instance of CDS, PGA, ADC and other beautiful stuff),
  • And 4 blocks at the corner, they can contain timing generation, reference generation, maybe ADCs if they are not implemented on the columns, etc.

During the normal design phase, one or more designers take care about all these separate blocks and at the end of the design process, all blocks are nicely put together, the design is checked and finally the complete lay-out is sent to the mask shop to fabricate the masks.  Such a mask set normally consists of several reticles/masks, and in most cases, every layer of the lay-out (active area, implants, poly-layer, contact openings, vias, metal layers, etc.) is put on a separate reticle/mask.  As an example, a “simple” CMOS imaging process consists of 30 reticles (or more).  The maximum useful area of a reticle, defined by the field of view of the lithographic equipment, is about 25 mm x 25 mm (the numbers given here are indications and differ from machine to machine).

The limitation of the reticle area is defining the maximum size of the chip, unless stitching is applied.  Stitching is a technology that allows the designer to fabricate an image sensor that is larger than the field of view of the lithographic equipment, still making use of reticles that fit into the field of view of that equipment.  Moreover, the size of the sensor will only be limited by the wafer size (and the budget of the customer).

To realize a sensor larger than the reticle size, the following strategy is applied : the very last stage in the design, being putting together the major building blocks as shown in Figure 1, is omitted.  The building blocks themselves are put on the reticle as individual pieces of the design.  This concept is shown in Figure 2.

Figure 2 : Isolated building blocks put separately on the reticle.

These building blocks cannot be used as separate circuits, they can only operate in connection with each other.  By appropriate programming the lithographic tool, each individual block of the reticle can be selected (by means of mechanical blading) and can be transferred into the photoresist on the wafer.  In this way it is possible to “stitch” the various blocks together on the wafer during the lithographic process.  But because the blocks are stitched during the wafer manufacturing process, it is also possible to make other configurations (than the one shown in Figure 1) by means of multiple use of the various blocks.  An example is illustrated in Figure 3, where the matrix of pixels is repeated 6 times.  To complete the sensor, several other blocks need to be repeated twice or threefold as well.  And in this way, an image sensor can be fabricated that is larger than the field of view of the reticle.


Figure 3 : Extending the size of the sensor beyond the reticle field of view.

If the design of the various blocks is carefully done to avoid stitching artifacts, then actually the final device shown in Figure 3, will look like the one illustrated in Figure 4.  The stitch lines will no longer be visible or noticeable, and the end result of the stitching technology is a large-size, monolithic image sensor.


Figure 4 : Final imaging array after stitching.

These days, stitching is widely applied in the digital imaging industry.  Various lithographic tools have different sizes of the reticle field of view, but in general terms, one can state that all full-format imagers (36 mm x 24 mm) or larger are stitched devices.

Albert, 08-07-2016.

Harvest Imaging Forum 2016 : update

June 21st, 2016

Registration is open since a couple of weeks for two sessions in December 2016, see www.harvestimaging.com/forum_introduction_2016.php

For those interested to attend, make sure you register a.s.a.p. for one of the two sessions, because this time there will be NO third session.

The Harvest Imaging Forum 2016 will be limited to maximum two sessions that each have a limited amount of seats.

Albert, 21-06-2016.


June 17th, 2016

Although most imaging engineers are aware about both technologies of butting and stitching, still some question marks exist about what is what ?  This blog as well as the next one try to give some answers to this question.

Butting is referring to tiling closely together separate pieces of silicon to come to one large sensitive array.  In principle all separate pieces of silicon can be operated as a single image sensor.  In most cases butting is used to make imagers that are larger than the largest imager a single wafer can hold.

Stitching is referring to putting various design blocks together during the processing of the silicon, to make one large, stand-alone imaging array.  All separate blocks of the design cannot be operated as a single image sensor, neither are they available as isolated dies.  In most cases stitching is used to make imagers that are larger than the field of view of the lithographic equipment used during the fabrication of the imagers.

Are all buttable devices also stitched ?  Most of them are, because in many cases stitching is needed to make the largest array possible on a single wafer.  If that imager is still not large enough, butting is the only solution.

Are all stitched devices also buttable ?  For sure not, because not all stitched devices have a wafer-level size.

In Figure 1 a simple sketch is shown of an imaging array : the pixel matrix is surrounded by a left-driving and right driving circuitry, a readout part at the bottom and some extra electronic circuitry at the top.


Figure 1 : Sketch of the floor plan of an image sensor.

This sensor is not designed to be butted, because the circuitry around the imaging matrix is preventing a contiguous larger imaging area when two or more devices are placed next to each other.  To make this device buttable, at the circuitry along at least one side needs to be removed in the design.  An example is shown in Figure 2, with the result after butting in Figure 3.

Figure 2 : One-side buttable imaging array.

Figure 3 : Two devices butted together based on the device concept of Figure 2.

As can be seen in Figure 3, the total light sensitive array is twice as large as the size of a single device.  Butting will never ever be perfect in the sense that there will always some pixels missing between the two pieces of silicon.  But in most applications, the number of lines (in Figure 3) of missing pixels is limited to a single line of pixels.  It has to be mentioned that devices that are butted normally do not use small pixels.  But pixel sizes of several tens of micro-meters are very common for buttable devices.

The limitation of the sketch in Figure 3 is clear : only a factor of 2 ins ensitive area can be gained by butting 2 devices.  If a larger sensitive area is needed, buttability needs to be possible along more than 1 side, for instance 2 sides, as shown in Figure 4.

Figure 4 : Two-sides buttable imaging array.

Figure 5 : Four devices butted together based on the device concept of Figure 4.

The same accuracy as mentioned before can be obtained along the butting lines : only one column or one row of pixels will be missing.  Notice the rotated arrangement of the dies in Figure 5.  From bottom left to bottom right, rows are becoming columns and columns are becoming rows, etc.  So a little extra data reshuffling is needed after readout, but after all, a factor of 4 can be gained in light sensitive area compared to a single die shown in Figure 4.

A buttable configuration with more flexibility can be found with devices that are 3-sides buttable, shown in Figure 6.


Figure 6 : Three-sides buttable imaging array.

All electronics needed to drive the sensor is no longer available at the sides, neither at the top of the chip.  But the drivers and timing circuitry is placed between the pixels themselves.  The lay-out of the chip is becoming more and more sophisticated, because as can be seen in Figure 7, butting does not allow any circuitry at the butting edges.

Figure 7 : Six devices butted together based on the device concept of Figure 6.

But the big advantage of this design is the unlimited butting capability in one direction.  Of course in the other direction the number of devices is limited to 2.

The latter architecture is widely used for medical (mainly CMOS) and astronomy (mainly CCD, slow shift towards CMOS) applications.  With today’s 300 mm wafer sizes, single monolithic sensors of 200 mm x 200 mm on a single wafer can be made.  And with the butting x mm (H) x 400 mm (V) are possible, where x is defined by the application and the cost of the assembled device. (With a rectangular footprint of the sensor instead of a square one, even larger butted imaging arrays are possible.)

What about 4 sides buttable ?  To my knowledge a 4-sides buttable device is never realized in CMOS technology, although there were some attempts in the past to build 4-sides buttable CCDs.  But the wiring and the connections to the outside world are becoming extremely complex and difficult.  And with the existence of 300 mm wafers, there is much less justification left to design and fabricate 4-sides buttable devices (maybe with the exception of astronomy applications).

Next time the focus will be on stitching,

Albert, 17-06-2016

Difference between binning and averaging (2)

June 3rd, 2016

In the previous blog the focus was on binning (charge, voltage and digital domain) in the case the readout noise was dominating over the photon-shot noise.  In other words, for the case of small signals or low light levels.  This time, the situation for a shot-noise limited condition is considered.  And actually the story can be very short : it does not matter when or where the binning is done, in all cases the result is exactly the same.

For the charge domain : if n x n charge packets are added together, each with m electrons, then after binning the final charge packet holds :

n x n x m electrons.

The photon-shot noise in each individual charge packet was

sqrt(m) electrons,

so the SNR for every individual charge packet was

SNR = m/sqrt(m) = sqrt(m).

After binning the total photon-shot noise is equal to

sqrt(n x n x m) electrons

and the SNR will be equal to :

SNR = n x n x m/sqrt(n x n x m) = sqrt (n x n x m).

After binning in the charge domain, the increase in SNR will be

sqrt(n x n x m)/sqrt(m) = n !

For the voltage domain or digital domain : if n x n signals are added together, each with m electrons, then before binning the output signal would have been k x m V or DN, with k being the conversion gain from input (charge) to output (Volts or Digital Numbers).  Then after binning the final signal will be

n x n x k x m V or DN.

The photon-shot noise of each individual signal before binning was

k x sqrt(m) V or DN,

so the SNR for the individual signal before binning was

SNR = (k x m)/(k x sqrt(m)) = sqrt(m).

After binning the total photon-shot noise is equal to

k x sqrt(n x n x m)

and the SNR will be equal to :

SNR = (n x n x k x m)/(k x sqrt(n x n x m)) = sqrt (n x n x m).

After binning in the voltage of digital domain, the increase in SNR will be

sqrt(n x n x m)/sqrt(m) = n !

Conclusion : if there is enough light so that the performance of the sensor or the camera is shot-noise limited, it does not matter how the binning is realized, charge domain, voltage domain or digital domain.  The increase of the SNR after binning is always equal to a factor n, being the kernel size in the case of n x n binned pixels.

Albert, 31-05-2016.