Archive for February, 2018

ISSCC2018 (3)

Thursday, February 15th, 2018

Yoshioka (Toshiba) presented a 20 channel TDC/ADC Hybrid SoC with 200m ranging LiDAR.  The goal of this work was to develop a LiDAR system that can work for short distances (urban driving situations) as well as for larger distances, up to 200m (high-way situations, but not for Germany, there you need even larger distances !).  The complete system relies on a “Smart Accumulation Technique” which was explained during the presentation, but which is too complicated to explain here in a few words.  The advantage of this SAT method is the combination of working at longer distances while maintaining image quality.  Special attention was given to the choice of the LiDAR quantizer circuitry.  A TDC is fast and consumes a small area, but acquires only the ToF info, while an ADC is compatible with the proposed SAT method, but overall a ADC is slow and consumes a large area.  But if it is difficult to make a choice, then implement both !  And that is what is done in this hybrid concept : the TDC is used for short distances (0 … 20 m), the ADC is used for larger distances (20 … 200 m).


Bamji (Microsoft) presented a kind of follow-on of the work presented a few years at ISSCC and very well described in JSSC (they got the Walter Kosonocky Award for this publication).  A 1 Mpixel ToF image sensor showed impressive results : 3.5 um pixels, GS, 320 MHz demodulation, modulation contrast at 320 MHz is 78 %, QE of 44 % at 860 nm, and with a per-pixel AGC to obtain HDR.  The device is realized in 65 nm BSI (1P8M) process.  Unfortunately it was not explained (even not in Q&A) how the GS with an efficiency of 99.8 % is realized.


Ximenes (TU Delft) presented a 256×256 SPAD based ToF sensor.  The device is made in 45 nm (then you should be able to guess who fabricated the chip) and is stacked on a 65 nm logic chip.  It was claimed that for the very first time the digital supporting part of the detector was fully digitally synthesized.  Pixel pitch is 19.8 um with a fill factor of 31.3 %.  The overall system allows a distance range of 150 … 430 m with a precision in the order of 0.1 % and an accuracy of around 0.3 %.


Gasparini (FDK) closed the session with a talk about a 32×32 pixel array for quantum physics applications.  The presenter tried to explain the concept of entangled photons, but I am not sure whether all people in the audience understood this concept after a full day of presentations.  The sensor is based on SPADs, each with its own quenching circuit and TDC.  The chip was realized in a low-cost 150 nm 1P6M CMOS standard technology, pixel size 44.64 um (with in-pixel time-stamping, not surprising if David Stoppa is one of the co-authors) and almost 20 % fill-factor.  Implemented are features to skip rows and frames to speed the overall imaging system.


Overall the imaging session of the ISSCC2018 was one of high quality, very well prepared presentations, great sheets (16:9 for the first time at ISSCC).  There was a large audience (the largest ever for the image sensor session at this conference), and during the Q&A long waiting lines were piling up in front of the microphone.

Take away message : everything goes faster, lower supply voltages, lower power consumption, stacking is becoming the key technology, and apparently, the end of the developments in our field is not yet near !  The future looks bright for the imaging engineers !!!

Albert, 15-02-2018.

ISSCC2018 (2)

Wednesday, February 14th, 2018

Kumagai (Sony) talked about about a 3.9 MPixel Event-Driven BSI stacked CIS.  It is not the kind of sensor that is being researched by the group of Tobi Delbruck, neither what is being done at Chronocam.  But in this new device, the data is reduced drastically by on-chip binning, column wise as well as row wise.  The overall resolution of 3.9 Mpixels is reduced to on 16×5 macro pixels.  In this “macro” pixel mode, the power consumption is drastically reduced as well, and the sensor behaves in a sort of sleeping mode.  Once the sensor detects any motion in the image (by means of frame differencing), the device wakes up and switches to the full resolution mode.  Also in the full resolution mode, the CIS works at 1.8 V supply voltage.  So that keeps the power consumption low, also in full resolution.  The device is realized in 90 nm 4CU CIS technology, on top of a 40 nm 1Al6Cu logic chip.  Pixels are 1.5 um x 1.5 um.  In full resolution, 60 fps, 10 bits, the device consumes 95 mW.  In sensing 16×5 macro pixel mode, the power is lowered to 1.1 mW at 8 bits and 10 fps.  Random noise is 1.8 e, resulting in a dynamic range of 67 dB at 10 bits and full resolution, and of 96 dB in the sensing 16 x 5 mode.


Chou (TSMC) explained the ins and outs of a 1.1 um CIS 13.5 Mpixel, 34 fps with switching options to 514 fps at 720p, 230 fps at 1080p and 58fps at 2160p.  The basic idea is to skip columns in the reduced resolution modes, while still using the full bank of column-level ADCs.  In this way 2 or 3 rows can be read out at the same time which increases the frame rate.  Because the different options to connect the columns to the ADCs, the interconnect is a bit complex, but of course the design and lay-out of the device has to be done only once.  Some numbers : technology used for the sensor is 45 nm 1P4M, for the logic 65 nm 1P5M.  Noise is 1.8 e, column FPN 0.28 e, full well 4458 e, resulting in a dynamic range of 67.5 dB.

Yasue (NHK) presented a new 8K4K device for ultra-HD broadcasting applications.  Needs to be ready to provide us with super quality slow motion pictures of Tokyo 2020 !  The sensor runs in a progressive mode.  Key characteristics are low noise (for that reason a 3-stage pipeline ADC is used), duplicated source followers with parallel operation (to speed up the device) and an ultimate speed of 480 fps (to realize the super slomo option).  The pipeline ADC consists of a folding integration stage, a cyclic stage and a SAR stage.  In 120 fps mode, the ADC works at 14 bits (noise is 3.2 e, 12.5 W), in 240 fps mode, the ADC works in 12 bits (noise is 4.3 e, 9.8 W)  and finally in the 480 fps mode, the ADC works in 10 bits (noise is 24 e, 9 W).  Apparently the specs are almost met in the 120 fps mode (target was 3 e of noise), but there seems to be room to improve at 480 fps.  Maybe next year’s ISSCC ?


Albert, 14-02-2018.

ISSCC 2018 (1)

Tuesday, February 13th, 2018

Sakakibara (Sony) presented a paper about a BSI-GS CMOS imager with pixel-parallel 14b ADC.  One can make a global shutter in a CMOS sensor in the charge domain, in the voltage domain, but also in the digital domain.  The latter requires an ADC per pixel (also known as DPS : digital pixel sensor).  And this paper describes such a solution : a stacked image sensor with per pixel a single ADC.  Based on the recent history of Sony technology, it could be expected that this technology was coming.  The ADC (per pixel !) is a single slope ADC with a comparator and a latch per pixel.  The design of the pixel is such that the source follower is already part of the comparator.  That makes the structure very compact, but requires two Cu-Cu contacts between top and bottom layer per pixel.  To get rid of all the data generated by all these ADCs, a pretty complex data line structure is implemented.  The technologies used : 90 nm 1P4M for the top layer, 65 nm 1P7M for the bottom layer.  Pixel size is 6.9 um x 6.9 um, 1.46 Mpixels, noise level 5.15 e in a high power mode of 746 mW @ 660 fps or 8.77 e in a low power mode of 654 mW @ 660 fps.  Dynamic range for the two modes is respectively 70.2 dB and 65.7 dB.  PLS for this global shutter is -75 dB.


Nishimura of Panasonic talked about the organic-photoconductive film GS CIS with an in-pixel noise canceller.  It is not the first time that this technology is presented at ISSCC, but this time an extra noise cancellation “trick”  is applied in the pixel to lower the noise.  Do not forget that this pixel is basically a 3T pixel that suffers from kTC noise.  A similar noise cancellation method was applied as what we have seen earlier with the so-called “active reset”, but no longer on column level, this time on pixel level. Key advantage of this device is the GS mode with very good PLS (- 110 dB), tunable sensitivity by biasing the right voltage across the photoconductor, very high saturation level.  The paper claims that the reset noise is lowered by a factor of 10, while the saturation level is increased by a factor of 10 (but the high saturation mode cannot be combined with the low noise level).  The pixel size is 3 um x 3 um, for a 8192 x 4320 pixels, 60 fps, 12 bit ADC, 65 nm process technology 1P4Cu1Al, noise of 8.6 e (in the proceedings, not consistent with the presentation where it was mentioned 4.5 e).  But again not a single indication about dark current and dark non-uniformities.  During the presentation as well as after the session, super quality images were shown, but all was prerecorded.


Choi of Samsung presented 24 Mpixel CIS with a pixel size of 0.9 um, using full-depth deep-trench isolation.  As can be expected, a 0.9 um pixel will suffer from full-well limitations, crosstalk and sensitivity issues.  Unless, a thickness silicon layer (40 % thicker, going from 3 um to 4.25 um, these last numbers are guesses !) is used (for this BSI device) in combination with DTI that goes all the way through the silicon.  So basically you create an isolated island for every single pixel (in the talk it was mentioned that if the pixels are fully isolated from each other by the DTIs, they can be operated at a lower voltage, which is in its turn beneficial for dark current and dark non-uniformities).  The sensor is using stacking with TSVs, and apparently the trenches are filled (with poly-Si ? not sure about this) and are biased with a negative voltage to keep the dark current low.  All techniques mentioned are not new, but their combination for a 0.9 um is new.  The author made a comparison between this new 0.9 um pixel and an existing 1.0 um pixel, and the new one beats the old pixel is all aspects : full well 6000 e, dark temporal noise 1.4 e, dynamic range 64.9 dB, dark current (60 deg.C) 2 e/s.  A strong reduction in white spots and RTS pixels is mentioned in the overview table, but it is not clear what is exactly done in the technology to come to these levels.


Albert, 13-02-2018.