Sakakibara (Sony) presented a paper about a BSI-GS CMOS imager with pixel-parallel 14b ADC. One can make a global shutter in a CMOS sensor in the charge domain, in the voltage domain, but also in the digital domain. The latter requires an ADC per pixel (also known as DPS : digital pixel sensor). And this paper describes such a solution : a stacked image sensor with per pixel a single ADC. Based on the recent history of Sony technology, it could be expected that this technology was coming. The ADC (per pixel !) is a single slope ADC with a comparator and a latch per pixel. The design of the pixel is such that the source follower is already part of the comparator. That makes the structure very compact, but requires two Cu-Cu contacts between top and bottom layer per pixel. To get rid of all the data generated by all these ADCs, a pretty complex data line structure is implemented. The technologies used : 90 nm 1P4M for the top layer, 65 nm 1P7M for the bottom layer. Pixel size is 6.9 um x 6.9 um, 1.46 Mpixels, noise level 5.15 e in a high power mode of 746 mW @ 660 fps or 8.77 e in a low power mode of 654 mW @ 660 fps. Dynamic range for the two modes is respectively 70.2 dB and 65.7 dB. PLS for this global shutter is -75 dB.
Nishimura of Panasonic talked about the organic-photoconductive film GS CIS with an in-pixel noise canceller. It is not the first time that this technology is presented at ISSCC, but this time an extra noise cancellation “trick” is applied in the pixel to lower the noise. Do not forget that this pixel is basically a 3T pixel that suffers from kTC noise. A similar noise cancellation method was applied as what we have seen earlier with the so-called “active reset”, but no longer on column level, this time on pixel level. Key advantage of this device is the GS mode with very good PLS (- 110 dB), tunable sensitivity by biasing the right voltage across the photoconductor, very high saturation level. The paper claims that the reset noise is lowered by a factor of 10, while the saturation level is increased by a factor of 10 (but the high saturation mode cannot be combined with the low noise level). The pixel size is 3 um x 3 um, for a 8192 x 4320 pixels, 60 fps, 12 bit ADC, 65 nm process technology 1P4Cu1Al, noise of 8.6 e (in the proceedings, not consistent with the presentation where it was mentioned 4.5 e). But again not a single indication about dark current and dark non-uniformities. During the presentation as well as after the session, super quality images were shown, but all was prerecorded.
Choi of Samsung presented 24 Mpixel CIS with a pixel size of 0.9 um, using full-depth deep-trench isolation. As can be expected, a 0.9 um pixel will suffer from full-well limitations, crosstalk and sensitivity issues. Unless, a thickness silicon layer (40 % thicker, going from 3 um to 4.25 um, these last numbers are guesses !) is used (for this BSI device) in combination with DTI that goes all the way through the silicon. So basically you create an isolated island for every single pixel (in the talk it was mentioned that if the pixels are fully isolated from each other by the DTIs, they can be operated at a lower voltage, which is in its turn beneficial for dark current and dark non-uniformities). The sensor is using stacking with TSVs, and apparently the trenches are filled (with poly-Si ? not sure about this) and are biased with a negative voltage to keep the dark current low. All techniques mentioned are not new, but their combination for a 0.9 um is new. The author made a comparison between this new 0.9 um pixel and an existing 1.0 um pixel, and the new one beats the old pixel is all aspects : full well 6000 e, dark temporal noise 1.4 e, dynamic range 64.9 dB, dark current (60 deg.C) 2 e/s. A strong reduction in white spots and RTS pixels is mentioned in the overview table, but it is not clear what is exactly done in the technology to come to these levels.
Albert, 13-02-2018.