Harvest Imaging Blog

Some thought about day 4 :

• a student presentation from Shizuoka university about a fully-depleted SOI based detector : the conversion part is located in the base substrate, while the circuitry is located in the thin top layer silicon of the SOI.  Very clever solution for this BSI sensor, although that some parameters still have some room for improvement,
• a stacked device from JPL with their delta-doped interface layer.  The latter gives a highly doped, ultra-thin top layer without any damage to the structure, resulting in a very stable device, even after radiation,
• Invisage presented a paper about their quantum dot based image sensor.  Finally some numbers were shown, the devices are characterized by kTC noise and (still) a relative large dark current (600 electrons/pixel/sec at 60 deg.C for a 1.5 um pixel pitch).  A very interesting feature of these devices is the fact that they can detect electrons OR holes, depending on the polarity of the bias voltage,
• Another quantum dot paper from imec, based on 6 nm PbS dots in a 3-layer film of a total thickness of 150 nm.  The authors showed some preliminary results, a 2D sensor is not yet realized.  Come and see at IISW2019,
• ISAE illustrated their further work on radiation hardening of CMOS image sensors.  In conclusion : a pMOS degrades faster than an nMOS, a PPD is not suited for Grad radiation tolerance, shallow diodes can withstand radiation better than deeper diodes and a 1.8 V architecture is the best if radiation hardness is concerned.
• Tower had a paper about different PD structures to enhance near-IR detection.  4 PD were compared : a 3 um deep diode, a 6 um deep diode, a 9 um high-resistivity and a 12 um high-resistivity substrate.  All results reported were done on a GS 2.8 um pixel.  Accutally all variations still suffer from optical cross-talk.  For that reason, in Tower’s 65 nm process, a stacked PD will be introduced : two structures on top of each other made in a double epi-layer and with an implanted isolation.
• Canon showed an improved version of their sensor that was already introduced at IEDM 2016 and ISSCC 2017.  A lightpipe and a double micro-lens were added over previous versions.  130 nm CIS process with 1P4M + LS, 3.4 um pixel, 79 dB dynamic range, 1.8 electrons of noise and PLS of -89 dB.
• A very similar paper came from TPSCo about double micro-lenses, but on a pixel of 2.8 um.  The presenter claimed that in the near future also light pipes will be added and that a PLS of 83.5 dB can be obtained.
• IMEC opened the GS session with a fully depleted device with 52 um pixels and with a charge transfer of 6 ns.
• A BSI imager with GS from ON semi, most probably with a storage node in the charge domain (a pixel architecture was not disclosed), and with a shielding of the storage node by means of implantations.
• ams (formerly CMOSIS) closed the workshop with a large area device having GS pixels based on their in-pixel voltage storage nodes.  47 Mpixels, 30 fps, 90/65 nm, only 2 layers of metal resulting in a total optical stack of 1.5 um, DTI and stitched in 1 direction.  Angular dependency of the light sensitivity was shown as well as angular dependency of the PLS (have never seen this before at a conference or workshop).

Albert, 02-06-2017.

Some thoughts about day 3 :

• Several ADC papers were presented, with a common motivation : hybrid ADC solution for the image sensor application : Tokyo Institute of Technology highlighted a SAR in combination with a delta-sigma ADC (without indicating the number of bits in their paper), University of Oxford combined a single-slope with a TDC solution to realize a fast 12-bit ADC, Teledyne DALSA presented a fast SS-ADC used in their TDI-CCD/CMOS combination, Teledyne Anafocus came up with a column-parallel solution based on two-stage oversampled converters, and finally Olympus presented a SS-ADC with a operation-period-reduced TDC to increase the conversion speed and keep the power consumption low.
• In between all those ADC papers, Delft University showed an on-chip digital calibration technique to correct the non-linearity of the pixels.  Actually this calibration technique is based on “shaping” the ramp of the SS-ADC, so also this paper was referring to ADC related stuff.
• In the final session of day 3 a collection of papers was presented on various topics.  JPL gave an overview and update of their latest image sensor work, university of Toronto talked about a CMOS architecture fo a so-called primal-dual coding with on-chip programmable masking techniques for the pixels (pixels are based on a good-old photogate), Sony re-presented their ISSCC paper on a stacked device with a very powerful 140 GOPS column parallel processing capability, and the session was closed by IMEC reporting a high-speed BSI version of their TDI CCD-CMOS combination.  Quite a bit of CTI-, noise-, MTF- and dark-current measurement data was shown in this last presentation with the comment of the speaker that there is still room to improve considering the performance of the device.

Albert, 01-06-2017.

Some thoughts about day 2 :

• two back-to-back papers of Dartmouth about the QIS.  The first paper described basically the work on a single Jot with reset-gate less pixel, with a tapered reset gate, with a JFET readout and with a buried channel readout, all fabricated in a stacked 45nm/65 nm BSI TSMC technology.  Some numbers : 1.1 um pixel pitch, 540 uV/electron conversion gain, best noise as low as 0.22 electrons.   The second paper talked about the integration of the Jots in an array.  The testdevice has 1 Mpixel.   The promise made : by 2019 they will show 100 Mpixel.
• the largest SPAD array ever was reported by EPFL, while the smallest SPADs came from University of Edinburgh.
• also the university of Edinburgh reported about the transformation of QIS bitplanes to compensate motion.  The paper was supported by spectucular images,
• Delft University presented a SPAD integrated on a flexible substrate with the capability of being sensitive from both sides of the device,
• a dedicated ToF session opened with a paper from Shizuoka University illustrating a 3-tap ToF sensor (normally 2-tap or 4-tap devices are shown),  also 3-taps in a paper of the University of Lyon in cooperation with ST and CEA-Leti.  The latter was made on a “doping-profile-controlled” epi-layer to enhance the transport of the electrons to the collection nodes,
• several years ago Samsung presented material on RGB-Z sensors, also at the workshop they showed an alternative concept for a RGB-Z device based on structured light with a green laser beam.  The device included a simple trick to cope with a large amount of background light : using the FD-RST combination as a logarithmic pixel.
• HDR was, is and remains a hot topic.  Apparently everyone is seeking a solution that does not suffer from motion artefacts.  This can be done by “playing” around with the gain of the output structure by adding an extra capacitor.  This idea can be found in the work of Brillnics (3 different conversion gains, 87 dB, 3.0 um pixel), ON Semi (extra in-pixel capacitor like LOFIC, 98 dB, 6 um pixel pitch), Caeleste (extra in-pixel capacitor in combination with extra gain in the columns, 92 dB, 12 um), ON semi (multiple reads of the PPD with storage on an external capacitor, 140 dB, 3 um pixel pitch), OmniVision (extra in-pixel capacitor, 120 dB, 2.8 um pixel pitch).  Apparently once the sensor does better than 120 dB, the sensor is no longer the limiting factor as far as DR is concerned,
• “out-of-the-box” is the solution proposed by ST : detection, collection and readout of electrons as well as holes.  The electrons are collected in the classical way (FWCe = 33000), the holes are stored in the capacitances of the DTIs which has a very large total storage capacitance (FWCh = 750,000).  Result : 116 dB dynamic range in a 3.2 um pixel pitch,
• between all the HDR stuff, Delft University presented a 0.5 electron noise device with correlated double sampling in the charge domain.  A conversion gain of over 1.5 mV/electron was reported measured on a device made in a standard 0.18 um CIS process,
• Ritsumeikan University calculated the temporal resolution limit of silicon imagers.  The result is around 11 ps.  So still a long way to go before we reach the maximum frame rate corresponding to this limit, being 90 Gfps,
• high-speed devices were presented by Tohoku University (based on burst mode with analog memories outside the active imaging area, 10 Mfps, 960 frames), Vrije Universiteit Brussel (burst mode based on in-pixel storage, 20 Mfps, 108 frames), Tokyo University ( 0.64 usec row-time), and AGH University of Krakow (70 kfps for a device with 75 um pixel pitch intended for XRD applications).

Sorry for any typos or for any missing papers, also day 2 had again a lot of information : 2 invited papers and 23 submitted papers !

Albert, 31-05-2017.

Some thoughts about day 1 :

• Sony showed that they are ready for hybrid bonding on pixel level with a pitch of 2 um (on teststructures) and 4 um in a real imager with 1 um pixel pitch,
• A collaboration between TSMC and Qualcomm illustrated a stacked image sensor on top of an FPGA,
• According to Omnivision, the pixel race is picking up again.  This was illustrated by an imager with a pixel pitch of 0.9 um, with the same performance as the 1.0 um pixel,
• Fermi Lab showed an very complex die-to-wafer-to-wafer structure,
• TSMC realized a 4T pixel in which the charge transfer (underneath the transfer gate) is no longer taking place at the interface but deeper into the silicon.  Also this was demonstrated in a device with 0.9 um pixel pitch with an improved noise performance,
• TechInsights give a great (historical) overview of PDAF pixels and stacking.  Although they tell what others are doing (or have been done), still a lot of interesting details were shown,
• BAE illustrated that dark current is reduced over the years by a factor of 5000, and that we now have a temperature behaviour according the Eg-law, while in the past it was the Eg/2-behaviour.  Unfortunately (or maybe fortunately), still not all dark current secrets are yet revealed,
• TowerJazz illustrated a pinned-storage node in a global shutter pixel with 2.8 um pixel pitch (is this global shutter CIS with 2.8 um seen elsewhere in a product of … ?)
• Fluorine implant is used to lower the noise in a CIS, this was presented by Dongbu,
• Random Telegraph Noise got quite a bit of attention, talks from TSMC and twice Tohoku University showed a lot of measurement results to further explain and understand the RTN effect,
• On-chip near-IR filter for colour imaging was presented by VisEra.  This is an attractive alternative to the classical near-IR filter because it makes the height of the camera-module lower.

It is impossible to write about every single paper.  On day 1 there were 17 presentations plus 45 posters, an incredible amount of details and information.  But the good news is that all papers will become on-line (open access on www.imagesensors.org) in about 2 or 3 months from now.

Albert, 30-05-2017.

The webpage for the new Harvest Imaging project, related to reproducibility, variability and reliability of CMOS image sensors is ready !

In this Harvest Imaging project the reproducibility, the variability and the reliability of the CMOS imagers will be analyzed :

• Reproducibility : will give quantitative information about how well particular measurements and retrieved performance data do reproduce if the devices are measured over and over again by means of the same calibrated measurement equipment,
• Variability : will give quantitative information about the spread of the performance data from sensor to sensor/from camera to camera,
• Reliability : will give quantitative information about the stability of the sensor and camera performance over time.

The measurements are done on a higher-end, more expensive camera with a global shutter CMOS sensor and on a lower-end, cheaper camera with a rolling shutter CMOS sensor. The cameras will be thoroughly measured every 6 months over a period of 5 years.  The yearly reports about the measurement results will become available in the Summer of each calendar year (Summer ’17, Summer ’18, Summer ’19, Summer ’20 and Summer ’21). A customer can step into this project at any given time, but the earlier the more attractive the pricing of the report(s) will be.  Once a customer has stepped into the project, he/she will automatically receive all reports that are produced AFTER the date he/she stepped in.

For more information, please check out : www.harvestimaging.com/newproject.php

Albert, 2/5/2017.

After the successful Harvest Imaging project on Phase-Detection Auto-Focus pixels (or PDAF), a new project is started that again will generate technical data about CMOS image sensors.  This time the focus will be put on the reproducibility, variability and reliability of the sensor’s performance characteristics.  This kind of information has never been published before.  None of the CMOS image sensor vendors is supplying numerical information about reproducibility, variability and reliability of their devices.  So if the vendors do not supply this data, only measurements on existing products can reveal the “secrets”.

Within a couple of weeks from now  more information on the tests performed as well as information on the parameters characterized will become available on this website of Harvest Imaging (www.harvestimaging.com).

So stay tuned !!!

Albert, 13-04-2017.

Recently we went for a ski holiday.  Because I do not have my own skis, I had to rent then, and below you can see what I got …… : RTS !!!!!

Albert 05-03-2017.

“A 0.44 e rms read-noise 32fps 0.5 Mpixel high-sensitivity RG-less-pixel CMOS image sensor using bootstrapping reset” from Shizuoka University was presented by T. Wang.  The device is using correlated multiple sampling (CMS) on column level in combination with a high conversion gain.  The latter is obtained by reset gate-less pixel and a bootstrapping technique.  The final result is a conversion gain of over 150 uV/electron.  The reset-gate less pixel is not really new, this is already published by the same group at other conferences.  By means of carefully designing the distance between the floating diffusion and the reset drain diode, the reset-gate less device can be operated.  But in this paper the extra bootstrapping technique is added to allow a larger voltage swing of the pixel.  Pictures of a scene illuminated at 0.1 lux were shown (after averaging 16 images !).  Pixel size is 11.2 um, with a full well of 4100 electrons.  The read noise is as low as 0.44 electrons rms.  Despite of the low full well, still a dynamic range of 72.3 dB is mentioned.

The last paper in the imaging session was entitled “A 1ms high-speed vision chip with 3D stacked 140GOPS column-parallel PEs for spatio-temporal image processing” by T. Yamazaki of Sony.  The device is really fully exploiting the capabilities of the 3D stacking.  In the second layer of silicon a memory is included next to column level processing elements and the column level ADC.  In this bottom silicon layer, filtering of the data can be done, as well as target detection, target tracking and feature extraction.  The speed at which all operations are done is simply phenomenal.  The imaging part is made in a 90 nm 1P4M process, the bottom part is made in a 40 nm 1P7M process.  Pixel size is 3.5 um, full well is 19,800 electrons, random noise is 2.1 electrons, resulting in 80 dB dynamic range at 12 bits.  As mentioned in the title, the processing in the spatio-temporal domain can be done at a speed of 1 ms.

Albert, 10-2-2017.

Tsutomu Haruta of Sony presented “A ½.3 inch 20 Mpixel 3-layer stacked CMOS image sensor with DRAM”.  In just a few words : the sensor is composed out of 3 layers : top layer contains the photon conversion part (BSI), the middle layer contains a DRAM and the bottom layer contains the processing part.  The first time that a stacked imager with 3 layers is shown.  The mutual connections between the various levels of silicon are realized by TSVs.  The image part can be readout very fast, much faster than the interface with the external world can handle.  So the DRAM is used as an intermediate frame buffer : fast readout of the imaging part and data stored in the DRAM, next a slow readout of the DRAM to accommodate the slow interface of the total system.  The pixels are arranged in a 2 x 4 shared pixel concept, with 8 column readout lines for two groups of 2 x 4 pixels.  4 rows of column level ADCs are included to allow the fast readout of the focal plane.  Remarkable is the fact that the data generated in the top layer has to be transported in the analog domain to the lowest level where the ADC is located.  Next the digital data is stored into the middle layer, being the DRAM.  It was not mentioned during the presentation, neither during Q&A, why the DRAM is located between the top and bottom layers.

With this particular architecture of the system, one can readout the sensor part extremely fast into the DRAM and one can readout the DRAM relatively slowly towards the outside world.  In this way artefacts of the rolling shutter are limited.  Once the data available in the DRAM, it is also possible to work in different formats, even in parallel with each other : full resolution, or limited resolution as a kind of digital zoom.  Another very nice feature of the sensor is its binning capability : by combining a binning on the floating diffusion with the binning in the voltage domain, the resolution of the imager can be drastically reduced.  If this reduced resolution image is then sampled at a high speed, stored in DRAM and retrieved at a lower speed, an “on-chip” slow-motion is created.  In the binned lower-resolution mode, it is possible to store 63 frames in the DRAM, captured at a speed of 960 fps.  Demonstrations of this feature during and after the presentation were showed.  Great images !

Some numbers : in total 17 layers of interconnect are used in the 3-layered stacked imager : 6M for the CIS (90 nm), 4M for the DRAM (30 nm) and 7M for the logic (40 nm).  The imager has 21 Mpixels, 1.22 um pixel pitch, DRAM has 1 G bit, and the interface is MIPI based.

Shiníchi Machida of Panasonic presented a paper entitled : “A 2.1 Mpixel organic-film stacked RGB-IR image sensor with electrically controllable IR sensitivity”.  Panasonic presented already a couple of papers with organic films on last year’s ISSCC.  But in this new presentation, 2 organic films are stacked on top of each other : the top one is sensitive to IR light, the bottom one is sensitive to RGB.  Both layers need a particular voltage across them to become light sensitive, and this light sensitivity has a particular step function.  Below a kind of threshold voltage the organic film is not light sensitive and this threshold voltage differs between the RGB (low threshold) and the IR (high threshold).  So if a large voltage is applied across the sandwich of the two organic films, both become light sensitive, if a lower voltage is applied across the sandwich only the RGB-film is becoming light sensitive.  In this way the light sensitivity of the IR-film can be switched on and off while the RGB-film is still active.  (Although the sensitivity of the RGB-film drops to about 50 % if the IR-film is switched off).  Overall an interesting feature that other imagers with classical pixels cannot shown.  Unfortunately (just like last year) no information was given about noise, neither about dark performance, otherwise a good presentation.

Albert, 9-2-2017.