As I mentioned already earlier, there were a few of “duo” presentations at the ISSCC. A second pair of papers that pretty nicely went together were two papers on global shutter sensors.
The first one came from Sony, in which a 10 Mpixel device was described. The novelty of the device was indeed the global shutter, based on a dual storage node in the pixel. As know the floating diffusion is not really a dark-current-friendly storage node, neither CDS-friendly. For that reason an extra in-pixel capacitor can be used between the transfer gate and the floating diffusion. This idea is not new, but in the Sony paper, this extra storage node is relatively small, so it will not occupy that much space. The extra storage node is only used for very small charge packets and the readout can be operated in the CDS mode. For larger charge packets, the extra storage node cannot hold all the charges, and part of it will spill over to the floating diffusion. So in that case a dual storage node is used : the extra in-pixel capacitor together with the floating diffusion. The latter cannot be operated with CDS, but that is not a real problem, because it plays only a role in the case the charge packet is large (read : and the noise is dominated by photon shot noise). By itself a simple and cleaver idea, BUT the sensor has a 2×1 shared pixel concept, so every photodiode is provided with an extra in-pixel storage capacitor, but for two photodiodes there is only one floating diffusion. In other words, the idea presented in the paper can only be applied if the sensor is used in a 5 Mpixel mode instead of the announced 10 Mpixel mode. To me this was a bit a disappointing conclusion of the paper.
The device is realized in a 90 nm technology with 1P5M plus a light shield (so is it 1P5M or 1P6M ?). During the Q&A more info was requested about the FPN and colour, but apparently the device cannot be used in colour mode.
The second global shutter device was presented by Tohoku University. It was mentioned to be a 1T pixel/s device (not 1 transistor but 1 tera pixel/s !). The device can deliver 10 Mfs in full resolution and up to 20 Mfs in half resolution mode. The imaging area has 400 x 256 pixels and every pixel has 128 analog memory cells. So the device does capture a limited number of 128 frames at high speed. The memory part is organized above and below the imaging array. The floorplan of the device looks like a split frame-transfer device (for those of you familiar to CCDs). The memory cells are made by two capacitors in parallel : poly-poly capacitor and MOS-gate capacitor, with one common poly-layer. The pixels are 32 um x 32 um, pretty large and have a PPD of almost 16 um in length. During the author interview I asked the presenter how he solved the issue of image lag within such a large pixel at such a high speed. Unfortunately I could not get the secrets unrevealed, the presenter promised to me that this will be presented at another conference. Technology used is 2P4M, 0.18 um, and at full speed the device dissipates 24 W. Be careful not to burn your fingers !
Amazing movies were shown to illustrate the capability of the high-speed global shutter device. Very impressive taking into account that the work is part of a PhD project. Congratulations !
More to come !
Albert, 27-02-2012.
>>”…BUT the sensor has a 2×1 shared pixel concept, so every photodiode is provided with an extra in-pixel storage capacitor, but for two photodiodes there is only one floating diffusion. In other words, the idea presented in the paper can only be applied if the sensor is used in a 5 Mpixel mode instead of the announced 10 Mpixel mode…”
No, the signal out is separated by different Tx timing, so it is still 10MP output…
Oh, not Tx, should be another gate before storage signal out. The interesting thing is its performance on lag and leakage~