Another nice pair of papers came from NHK and Samsung. Especially their ADC attracted my attention : both papers made use of what I call myself a tandem-ADC. This is an ADC that is build around two different architectures or two different working principles. Last year’s ISSCC had already such a device in a Sony sensor, in which the column ADC was split into two parts : one with counter and one without counter if I remember well.
This time, NHK presented a very similar paper as the one presented at the International Image Sensor Workshop. It is a 33 Mpixel UHDTV sensor with pixels of 2.8 um x 2.8 um, that is capable of operating at 120 fr/s. The ADC used was split into two parts, both are cyclic ADCs, delivering in total 12 bits. The first 4 upper most bits are converted in a first cyclic ADC (based on 3 cycles), the last 8 lower most bits are converted in a second cyclic ADC (based on 8 cycles). These two cyclic ADCs operate in a pipelined organization, in this way extra speed can be gained.
The second presentation, Samsung’s, discussed a 24 Mpixel APS-C size imager with 3.9 um x 3.9 um pixel size. The on-chip ADC has a resolution of 14 bits in a full range of 1.7 V. The circuit realizing the first 2 … 6 bits, in combination with the CDS, is based on a delta-sigma converter. The remaining 8 bits are converted in a cyclic ADC. But actually the beauty of this construction is the fact that part of the delta-sigma and the cyclic ADC use the same building blocks. And because the two parts work in series, several building blocks of the delta-sigma are used as well in cyclic ADC. In this way the circuitry needed to realize the complete ADC remains relative small. Cleaver idea !
Talking about ADCs : Delft University of Technology presented a paper on a column-level ADC capable of doing multiple sampling without any increase of hardware. The ADC is based on an up-counter with BWI (Bit-Wise-Inversion) to allow digital CDS. In case multiple sampling is applied, the counters simply continue the counting for several consecutive samples. Without any special pixel design, the multiple sampling (in combination with an extra column amplifier) resulted in a noise level of only 0.7 electrons. The low conversion gain of the pixel (< 50 uV/e-) clearly indicated further room for improvement. Pixel noise levels of 0.28 electrons fabricated in “standard” CIS processes are needed for single-electron/photon detection. This performance level is coming closer !
More to come ? Maybe !
Albert, 28-02-2012.