ISSCC 2016 (3)

In this third and last review of the ISSCC, 2 remaining imaging papers are left.

The first one comes from NHK, and deals with a 1.1 um 33 Mpixel device, 3D stacked and 3-stage cyclic-based ADC.  This 3D stacking is realized by means of direct bonding (in the columns).  TSV’s are avoided because they seem to be too expensive, they cost more masks, they consume area and they make a more complicated lay-out needed.  The device is fabricated at TSMC (at least TSMC is mentioned in the acknowledgement), and to my knowledge this is the first CMOS image sensor made in 45 nm 1P4M.  The logic part on the second level of silicon is made in 65 nm 1P5M technology.

The ADC implemented on the chip (by Shizuoka Univ./Brookman Technology) is a three stage design, the first two stages are cyclic ADCs (upper 3 bits and middle 6 bits), the last stage is  a SAR ADC (3 bits).  The sensor can run at full resolution (33 Mpixels !) at a rate of 240 fps, burning 3 Watts.

The last paper from the imaging session is the one that was published by FBK, Trento, with two brothers as authors (does not happen that often).  The device presented is intended for spacecraft navigation and landing.  It contains 64 x 64 pixel digital silicon photomultiplier direct ToF with 100 Mphotons/s/pixel background rejection.  Every pixel (out of the 64 x 64 array) contains 8 SPADs  with extra electronic circuitry.  The pixel is designed such that uncorrelated photons or dark current (which still trigger the SPADs) do not give an output from the pixel.  Only correlated photons give an output.  So the background suppression and dark count suppression is more or less based on the statistics of these signals (compared to the ToF signal), and is implemented in the digital logic within every pixel.  Fabrication technology is 150 nm CMOS with 6 metal layers.  Pixel fill-factor is 26.5 %.

Albert, 08-02-2016.

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