At ISSCC several high resolution imagers were presented. Champion was the device of CMOSIS with 391 Mpixel device for airborne mapping applications. The device itself is pretty straight forward with 3.9 um pixel pitch, 4T non shared pixels, 31.5 ke– full well, 45 uV/e– conversion gain, 3.7 e– of noise at unity gain, resulting in 78 dB dynamic range. The 14-bit SS ADCs are placed in the columns and are located at the two sides of the imager. So the pitch of the ADCs is 7.8 um. Jan Bogaerts showed impressive images of the device, and after the “show” I had the opportunity to take a look at a real device in its package. The sensor is using stitching : 6 x 3 blocks are stitched in the active area, with 4352 x 5000 pixels in each stitched block. Processing was done at ST in a 90 nm FE/65 nm BE process 1P4M. The device is monochrome, but in the final application, this monochrome sensor is surrounded by CCDs that provide the colour information. During Q&A it was mentioned that the camera is using a mechanical forward motion compensation technique to compensate for the movement of the camera during exposure.
During the presentation Jan Bogaerts made a comparison with a CCD of the competition. Amongst several characteristics, he mentioned that his CMOS sensor is free of smear in contradiction to the CCD. In a private discussion afterwards with Jan Bogaerts he told me that the camera is using a mechanical shutter (that is no secret I guess), but one should realize that in that case a CCD is neither showing any smear issues.
Hirofumi Totsuka of Canon presented a 250 Mpixel APS-H size imager : 1.5 um pixel pitch (4 sharing) made in 0.13 um technology node. The device is consuming 1.97 W at full resolution 5fps. An interesting build-in feature of this sensor is the following : ALL pixel signals are converted by column SS-ADCs with a single ramp, but in front of the ADC, each column has its own PGA that can be switched to 4x or 1x gain, depending on the signal level. So when the pixels are sampled, a first check is done to look whether the signal is above or below a particular reference level, and then the right gain of the PGA is set to 1x or 4x. Simple method, but I think that the issues pop up in the reconstruction of the signal at the cross-over point between the two settings of the PGA.
Kei Shiraishi of Toshiba presented a stacked sensor with 1.2 e– of noise with a comparator-based multiple sampling PGA. The most important characteristic is the multiple sampling in the analog domain. This goes much faster than the multiple sampling in the digital domain. After 32 samples of each signal, a noise level of 1.2 e– could be reached for 1 M pixels at 20 fps. The device is realized in 65 nm, both for the sensor as well as for the circuit on the second silicon level. It was mentioned in the paper, but I guess that the noise floor without the multiple sampling should be around 5 e– at 30 fps, going down to the 1.2 e– reported at 20 fps.
Charles Liu of TSMC showed the results obtained by a 33 Mpixel, stacked device with a negative substrate bias. The idea is actually pretty simple, maybe the implementation is more complicated. “Simply” bias the substrate of the sensor to -1.3 V and you can lower all other supply voltages by 1.3 V. So instead of having a power supply of 3.3 V, the device has now a supply of 2.0 V. But the large pixel swing is maintained by means of the negative substrate bias. The sensor is fabricated in 65 nm 1P5M technology.
Albert, 05-02-2016.