This time a bomb of technical data and numbers is thrown out !
First one is coming from the presentation of Hiroshi Shimamoto (NHK). Their ultra-high definition camera was presented with the sensor having the following specs :
– 7680 x 4320 pixels, 2.8 um x 2.8 um pixel size, 120 fr/s, 12bit resolution ADC, prgressive scan, 8000 ADCs on-chip, conversion tims < 1.92 us, power < 3W, noise < 6 electrons, 96 LVDS outputs in prallel, 0.18 um technology, 1P4M, PPD pixels, 3/2″ optical format, 61.3 dB dynamic range , 0.66 V/lux.s sensitivity, full well < 10,000 electrons.
The key component of the chip is the column-parallel two-stage pipelined cyclic ADC, being an optimum compromise between speed, power and area. The ADC was already extentively highlighted during ISSCC2012. The complete readout of 1 line of information takes up 4 line times : 1) CDS of the column information, 2) conversion of the first 4 bits, 3) conversion of the 8 last bits, 4) reading off chip the digital data.
Here are more numbers, coming from Renato Turchetta’s talk about the work done at Rutherford Appleton Labs.
– X-ray detector based on a stitched mask set (thanks for giving the right reference !) : 14 um x 14 um pixel size, 4k x 4k pixels, 40 fps, 0.35 um CMOS technology, 3T, radiation hardness till 20 Mrad, analog out, on-chip binning and ROI options,
– wafer scale sensors : 2800 x 2400 pixels, 50 um x 50 um, 32 analog outputs, 40 fps, 139.2 mm x 120 mm, 6.7 Mpixel,
– sensors for synchrotron application : 4k x 4k, 25 um x 25 um, 120 fps, HDR with 1: 100,000 at 500 eV, this is still work in progress.
Besides all the data shown by Renato, he also introduced a very nice (and apparently very well received) idea of growing scintillators in cavities etched in silicon. In a silicon wafer (225 um thickness) holes are being etched (hexagonal in shape and 25 um in size), next in these holes a scintillator is grown. In this way the conversion and capture efficiency for the visible photons generated by the scintillator is increased.
Also Mark Downing (ESO) had a lot of numbers to report about a CMOS device that will be used in an adaptive optical system to be placed on the biggest telescope of ESO, being 39.5 m in diameter. The sensor characteristics :
1760 x 1760 pixels, 24 um x 24 um, 0.18 um technology, 6 metal layers, BSI, 4T pixels, 100 uV/e conversion gain, 4k electrons FW, 3.0 e noise, QE > 90 %, image lag < 0.1 %, Peltier cooled to -10 deg.C, power consumption < 5 W,
The chip has in total 70,000 (seventy thousand, this is not a typo) ADCs to comply with the required speed specificiation. These 70,000 ADC-SS allow to process 40 lines in parallel and offer the option to work at 700 fps. 88 parallel LVDS channels bring the data to the outside.
Albert, 23-03-2012.