Day 4 of the International Image Sensor Workshop in Hokkaido, Japan

The last day of the workshop contained only two sessions : the first one on global shutter pixels and the second one on high-speed and ADCs.

It is clear that a lot of effort is done in the direction of global shutter pixels.  The rolling shutters of the CMOS imagers is still a disadvantages compared to the global shutter of the CCDs.  Nevertheless the performance of the global shuttered CMOS pixels is constantly improving.  The world’s first global shutter in combination with back-side illumination was presented.  The pixel is an 8-transistor cell and to realize the global shutter, the information is stored in the voltage domain on an external-to-the-silicon capacitor.  This leads to a very high shutter efficiency of 1/110,000.  This presentation did perfectly fit into the scope of the workshop, being : discussing work in progress.  Although the shutter efficiency is already pretty high, the back-side technology presented needs further improvement.  But is should be encouraged that people are willing to show their results in a very early stage of their projects.  This leads to interesting discussions ! 

Completely opposite to-work-in-progress was the next presentation based on a product of a 1.2 Mpixel global shutter sensor with automatic gain selection.  This pixel makes use of 5 transistors and the in-pixel storage node is realized as a MOS-capacitor with storage in the charge domain.  The shutter efficiency is not as good as the one reported in the previous work, but on the other hand, the pixel is also much smaller, being 3.75 µm.  It was claimed that this is the smallest pixel in the industry with a global shutter. 

Also interesting was the presentation in which a high-speed column-parallel CMOS image sensor was developed with a SA-ADC based on the PTC.  First time I see the “PTC” in the definition/name of an ADC.  A similar idea was also implemented by one of my PhD students : apply a very fine ADC step when needed (= low-light levels) and allow a very coarse ADC step when allowed (= noise dominated by photon shot noise).  The ADC is capable of resolving 16 bits at the lowest segment with a conversion time of only 2.475 µs.  Papers on multiple windowing, global pipelined shutter CMOS devices, 2-stage pipelined cyclic ADCs  followed.   Apparently dividing the ADC workload in multiple steps seems to be the way to go for high-speed applications.  This was also described in the last two papers of the workshop.

Overall this was a great workshop !  An high-level technical program, superb organization and great service.  Thanks very much to our Japanese friends who were responsible for the organization of the workshop under extremely difficult conditions.  CONGRATULATIONS and THANKS VERY MUCH to Nobu, Junichi, Shoji and all others that contributed to the success of the workshop !

Tomorrow no more news.

Albert, June 14th, 2011

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