At the International Solid-State Circuits Conference a one-day forum was organized and chaired by Johannes Solhusvik (Aptina) entitled : “High-Speed Imaging Technologies”. An appealing program was put together, and here I would like to list a few highlights. After the opening by Johannes, the following topic were discussed :
– Boyd Fowler (Fairchild Imaging) : “High Speed CMOS Pixel Physics and Electronics”. Boyd’s talk showed that high-speed imaging is more than just a fast readout ! From his presentation the following lessons could be learned :
o QE and MTF are inversely related : a larger QE needs to allow collection of deeply generated electrons, but unfortunately deeper generated electrons will freely diffuse through the non-depleted substrate and cause contrast losses,
o carrier transport needs to be dominated by drift for high-speed detection, if the carrier transport is dominated by diffusion, it will take too long before the carriers are collected in the diodes,
o lag must be eliminated during carrier transport,
o digital readout (in-pixel ADC) is about an order magnitude faster than analog,
o high speed sensors need to be fully depleted on a thin substrate, this is basically a combination of the aforementioned arguments.
Some of these statements were illustrated by means of simulations.
– Jan Bosiers (DALSA) : “High-Speed Imaging with CCDs”. His talk contained details about :
o high-speed operation of CCDs in general,
o high-speed readout architectures,
o high speed capture concepts and
o details about a high speed CCD imaging sub-system.
Jan’s talk contained quite some details about the ISIS sensor of prof. Etoh (fabricated by DALSA). This device (with BSI !) is capable to capture 1 M frames per second. Great animations (with an NHK camera) showed the capabilities of this camera and sensor.
– Guy Meynants (CMOSIS) : “High speed CMOS image sensor architectures”. In his talk Guy addressed the following topics :
o High speed CIS architectures with an analog output, focusing on column load schemes, track-and-hold circuit, column amplifier, multiplexer design, ROI readout, column bus construction, analog buffers and power multiplexing,
o High speed CIS architectures with ADC on-chip, with column ADC, global shuttering.
Guy’s conclusion was actually straight forward : parallelism is heavily applied to speed up the devices. He illustrated this with many examples and with a nice demo at the end of his talk.
– Shoji Kawahito (Shizuoka University and Brookman Technology) : “Column readout circuit design for high-speed low-noise imaging”. The following items were addressed :
o Analog versus digital column readout,
o Column readout with preamplifier,
o Columns level ADC with accelerated readout timing,
o Source follower noise analysis,
o Column ADC with preamplifier and CDS,
o Column parallel ADC architectures,
o Digital CDS
o Figure of merit of column ADC and imagers.
Will be continued,
Albert 14-02-2010.