Wednesday Feb. 10th 2010 : Image Sensor session at the ISSCC2010.
The following papers were presented :
– Y. Chae et al. (Yonsei University and Samsung Electronics) : “2.1 Mpixel with column-parallel ADC architecture”. The speaker made an overview of the column level ADCs used in CMOS imagers : single slope architecture is too slow, the successive approximation has an area issue, and the cyclic ADC consume too much power. Apparently there is a need for another architecture ! A 2nd order Delta-Sigma ADC is implemented for the very first time as column-level ADC in a CMOS imager. The circuitry per column is 4.5 um wide and 600 um long, it contains 320 transistors and consumes 55 uW/column. A 2.1 Mpixel sensor is realized with the following characteristics : 2.25 um pixel, 2 sharing, 11000e- full well, 80 uV/e-, 0.013 % column FPN, 75 dB dynamic range, 180 mW @ 120 frames/s, 0.1 % non-linearity. The noise is as low as 2.4 e- at maximum frame rate and 1.9 e- at 130 times ADC sampling. The latter is an improvement of 54 % compared to the same device with a single slope ADC.
– Y. Lim et al. (Samsung Electronics) : “1.1 e- Noise CMOS imager with pseudo-multiple sampling”. Very simple idea with surprising results : instead of using one high-resolution ADC, the ADC conversion is divided into several lower resolution ADCs. The latter are realized as single slope ADCs with the possibility of multiple up- and down-ramps to create the multi lower resolution ADCs. In this way a kind of multiple sampling is realized and consequently the noise is being reduced. The device is realized in a 90 nm technology, 2.5 T shared pixel of 1.4 um, 110 uV/e- conversion gain, and 4100 e- full well. Sensitivity of 3700 e-/lux.s and a dark current of 6.4 e-/s @ 55 oC. At a frame rate of 6 fr/s a noise level of 1.1 e- was obtained with 12 bit ADC and 16x gain.
– K. Yasutomi et al. (Shizuoka University) : “CMOS imager with dual global shutter pixels”. It is known that with a 4T pixel in global shutter mode, the device suffers from noise issues : the leakage current of the floating diffusion is very high and in global shutter mode, CDS is no longer possible with a 4T pixel. For that reason, the authors have implemented a double shutter in the pixels. The first shutter implementation is a storage node between the pinned-photodiode and the floating diffusion. This storage node is a kind of pinned-photodiode as well to keep the dark noise as low as possible. Unfortunately the storage capacity is pretty small. So these characteristics allow this first storage node to be used in the case of very small signals. To transfer the charges from the pinned-photodiode into the storage node, the voltage in the storage node needs to be higher than in the pinned-photodiode, so the storage node has a different doping concentration. (Interesting to realize that foundries are willing to change/add these implants even for university experiments !) The construction of the storage node looks very similar to a virtual-phase CCD cell. For larger signals, when the noise of the shutter node is less important, a second shutter architecture is used, being the classical one : storage on the floating diffusion. These two storage nodes are designed fully in parallel. Results : shutter efficiency of the first shutter is 99.7 %, of the classical one it is 99.9 %, dark current of the first shutter is 119 e-/s @ 27 oC and is 1221 e-/s for the second one, also at 27 oC. The pixels are 7.5 um in size and have a fill-factor of 25 %. Full well is 10000 e- and the conversion gain is 38 uV/e-.
– C. Posch et al. (Austrian Institute of Technology) : “Address event PWM image sensor with lossless pixel-level compression”. Every frame in a video sequence contains a lot of redundant information, and based on that knowledge the authors created a kind of device that only outputs changes in the scenery. In this way a large amount of output data can be reduced, without any loss in information. The pixels become quite complex : 77 T, but the data reduction factor is quite impressive : up to 400 fully lossless. During the presentation a very nice video demonstration was shown to illustrate the working principle of the device.
Will be continued !
Albert 2010-02-11
Junichi Nakamura published the first 2nd order sigma delta ADC for column-parallel image sensor ADC some 13 years ago in IEEE Trans ED Oct 1997. It was a joint Olympus-JPL paper.
First I cited the paper of J. Nakamura et al. While the paper of Nakamura et al describes the first second-order sigma-delta modulator in an imager, my work describes the first imager with a column-level sigma-delta ADC i.e a sigma-delta modulator with a co-integrated decimation filter. This is a significant step because it facilitates full column integration.