Being the Technical Program Chair of the ISSCC2010, yesterday morning (Monday Feb. 8th 2010) I had the honor to officially open the conference. It was the first time in my life to speak in front of an audience of 2600 attendees. Very impressive view looking from the podium over such a crowd of people.
At the International Solid-State Circuits Conference one of the four plenary talks was delivered by Tomoyuki Suzuki of Sony (Senior VP). He gave an amazing overview of Sony’s history in the CCD field. We all know that Sony has a long track record in high-performance CCD imagers, but nevertheless the improvements Sony implemented in the CCD technology is quite impressive. Just to name a few (not necessarily all are invented by Sony but all are used in their products) :
– 1987 : vertical overflow drain allowing an anti-blooming in the third dimension, without losing any fill factor in the pixel,
– 1987 : HAD sensor, being the hole-accumulation diode or the pinned photodiode, with the capability of instant charge reset,
– 1987 : on-chip colour filters,
– 1989 : high energy implanter to allow a deeper p-well for the CCD, resulting in a better smear and a higher quantum efficiency,
– 1989 : on-chip microlenses,
– 1995 : on-chip colour resist filters,
– 1995 : epitaxial wafers to reduce cross-talk and smear,
– 1997 : inner lenses being a second microlens,
– 1997 : gapless microlenses,
– 2000 : double inner lenses,
– 2000 : tungsten light shield for an improved smear engineering,
– 2004: single layer transfer electrode, to increase yield and surface flatness of the sensors, resulting in a better angular response,
– 2008 : new wiring technology for the electrodes aiming for high-speed imaging.
Looking through this list it must be possible to imagine or visualize the 3D stack of which the photodiode is part of. Such a CCD pixel is a beautiful example of vertical integration starting deep in the silicon and extending several micrometers on top of the silicon.
Looking towards CMOS imaging, Suzuki-san named the following challenges :
– Pixel shrinkage, for which he suggested to move from aluminum interconnects to copper interconnects, this will drastically decrease the optical stack on top of the silicon. Although this technique is not really new, he showed beautiful SEM cross-sections of the pixel structures,
– Frame rate, for which he highlighted the column-level ADC architecture implemented by Sony and based on an up/down counter in every column, this work was awarded with the Walter Kosonocky Award in 2007,
– Sensitivity of the small pixels for which he showed results of Sony’s back-side illumination technology. He also showed some data coming from a new 10.3 Mpixel CMOS imager with 1.65 um pixel size : sensitivity almost 10,000 e–/lux.s, saturation : 9130 e–, conversion gain 75 uV/e–, 1.7 e– rms noise in dark (gain 16x), dark current 3 e–/s at 60 oC, and a dynamic range of 71 dB. Also of this sensor a very nice SEM cross section was shown which revealed some interesting details of the technology.
The following near-term trends for CMOS imagers were reported :
– Ultra high speed,
– Global shutter,
– Wide dynamic range,
– Increasing depth of field.
At the end of the talk Suzuki-san referred to two new future imaging functions being 3D imaging and curved image sensors. In other words, an interesting future is lying ahead of us !
Albert 09-02-2010