University of Toronto in cooperation with Synopsys and FBK presented “Dual-tap pipelined-code-memory coded-exposure pixel CMOS image sensor for multi-exposure single-frame computational imaging” (try to explain this to your mother !). The basic idea comes down to the fact that with a coded aperture quite some information is thrown away (e.g. 50 %) when a particular aperture is opaque for the incoming light. Only when the aperture is transparent, the incoming information is used. In this paper, a pixel is presented that has one large PPD and two TG-FD-SF combinations. The information is read out and accumulated through the first FD or through the second FD. In this way no incoming photons are lost. The content of the first FD can be seen as a kind of complement to the content of the second FD and vice versa. The pixel looks very similar to some pixels presented in ToF applications. But for the coding (switching between the two FDs), an in-pixel memory is needed. That is composed out of two latches. The pixel size is 11.2 um, a fill factor of 45.3 % is achieved, 27 % of the pixel area goes to the memory and extra logic in the pixel. The contrast between the two taps is reported to be 99 % at 180 fps. The device is fabricated in a 110 nm CIS process.
Applications mentioned for this sensor are one-shot structured light, one-shot photometric stereo, compressive sensing, etc.
The sixth paper in the session came from Panasonic : A 400 x 400 pixel 6 um pitch vertical avalanche photodiodes (VAPD) CMOS image sensor based on 150ps-fast capacitive relaxation quenching (RQ) in Geiger mode for synthesis of arbitrary gain images”. The main goal of this work is to incorporate a single photon avalanche photodiode function into a conventional CMOS image sensor pixels. The pixel proposed in this paper looks identical to a 4T pixel, except that the PPD is replace by an avalanche photodiode. Because the gain of the avalanche photodiode is not known, it looks like that the application for this device is limited to binary images, which can be used in time-of-flight, surveillance, AI and robotics.
The next paper was presented by Univ. of Edinburgh in cooperation with ST and Heriot-Watt University : “A 246×256 40nm/90nm CMOS 3D-stacked 120dB dynamic range reconfigurable time resolved SPAD imager”. The design challenges seen by the authors are (1 Mpixel SPAD @ 100 MCps/pixel in high background conditions) : 100 Tphoton events/second. Being more than 1 Pb/s (10 bits conversion) and 50 W TDC power. The presentation was built-up to highlight the advantages of SPADs (time resolution, no ADC, high dynamic range, single photon sensitivity, low median dark noise) and to counteract the disadvantages of SPADs (power consumption, TDC area, high I/O data rate, low fill-factor, many hot pixels.
During the presentation all the drawbacks were addressed one after another and solutions were proposed and implemented to counteract them :
- Stacking of the backside illumination SPAD above the readout IC (40 nm/90 nm process) is solving the fill factor issue, (pixel pitch of 9.2 um),
- In-pixel histogramming reduces the I/O data rate,
- The pixels are composed out of multi-SPADs with the option to inhibit pixels with a large dark current count (also called “screamers”),
- An event driven clocking is reducing the power consumption,
- Implementation of compact TDCs, ring oscillator based in combination with shift-register and counters (TDC area of 130 um2).
Albert, 21-02-19