“A Data Compressive 1.5b/2.75b Log-Gradient QVGA Image Sensor with Multi-Scale Readout for Always-On Object Detection” by Stanford Univ. and Robert Bosch.
Object detection in the classical way can be done by the combination of a convolutional neural network connected behind an image sensor. But that solution is pretty power hungry and not really suited for an always-on application. This paper suggests to do a coarse detection and feature extraction right after the sensor and if something is detected, a wake-up signal is generated to activate a convolutional neural network. The image sensor with the coarse detector and feature extractor (in the analog domain) are integrated on the image sensor chip. A very popular feature extraction is based on a so-called Histogram of Oriented Gradients (HOG). So one tries to find for 8×8 pixels the orientation of the gradient in the image data, and this method can be repeated for multiple scales of the image.
The trick of the HOG implementation in this paper is not looking after the difference in image values to detect an orientation in the image data, but to go after the logarithmic ratio of pixel values in the image data. Making ratios instead of differences makes the concept invariant to the illumination level. Simple, but very effective idea. The log gradients can be quantized to 1.5 bit or 2.75 bit and still being robust to illumination levels.
The design highlights of this device are recognized as : the log-gradient image sensor using standard 4T pixels in a Q-VGA configuration, compressing the data to 1.5 bits or 2.75 bits, being a 25 x data compression; option for pixel binning at the readout for multi-scale object detection; column parallel ratio-to-digital converters to digitize low resolution ratios of the pixels.
If it comes down to performance numbers, an energy per pixel of 127 pJ is reported, 0.13 um 1P4M process, pixel size of 5 um. Example images were shown to proof the concept of the image sensor.
“A 76mW 500fps VGA CMOS Image Sensor with Time-Stretched Single-Slope ADCs Achieving 1.95 e– Random Noise” by Yonsei University. Single-slope ADCs on column level, are widely used in CIS. So everyone knows the advantages, but also the disadvantages of requiring a lot of clock cycles. In the case one wants a fast conversion rate of for instance 1 us, a clock frequency in the GHz range is needed. This paper tries to find a solution for this issue, a kind of hybrid ADC is proposed. In the case of a 10 bit ADC, the 6 most-significant bits are converted by a classical single slope ADC. What is further measured (to find the 4 least-significant bits) is the time between the toggling of the comparator and the next clock cycle of the single-slope ADC. The toggling moment of the comparator is the start of the so-called time stretching activity. The end of the time stretching activity is equal to the falling edge of the ADC clock divided by 16. Why divided by 16 ? For the simple reason that in that case the original clock of the ADC can also be used to measure the number of clock cycles in the time stretched period. Very simple, very clever idea ! The total amount of pulses in the new ADC (10 bits) is now 64 cycles for the first 6 bits, and maximum 16 cycles for the time stretched value. In total 80 cycles instead of 1024 (12.8 x faster !), and a conversion of 0.8 us can be realized by a clock of 100 MHz. The new ADC not only results in a faster device, but also it consumes much less power (76 mW instead of 365 mW with the standard SS-ADC).
The reported device is a VGA sensor with 4 um pixel pitch, fabricated in 110 nm 1P4M technology. The noise values listed are 1.95 e– with a gain of 8, 2.85 e– with a gain of 1.
Albert, 20-02-19