SmartSens presented a paper entitled : A stacked global-shutter CMOS with SC-type hybrid-GS pixel and self-knee point calibration single-frame HDR and on-chip binarization algorithm for smart vision applications. This was a paper describing an image sensor in which several already known ideas are combined. The pixel of the imager is more or less the same as the one that is used by CMOSIS (now ams) : a global shutter pixel with the storage node in the voltage domain. Actually two storage nodes to sample reset and signal values to allow CDS. Where the CMOSIS pixel has an in-pixel current source for the first follower, the SmartSens pixel has instead a row-select switch to allow the pixel to run in a rolling mode without the extra sampling in the pixel for the global shutter mode. So you can run the pixel in rolling or in global shutter mode (that refers to the word hybrid in the title of the paper).
HDR is obtained by biasing the TX gate at two levels during the exposure time. In the first part of the exposure time TX gets an intermediate value which limits the full well of the PPD, and in the second part of the exposure time TX gets a low value to increase the full well of the PPD. Also this is a known technique, and it is also known that the creation of a knee point in the output characteristic will create great fixed-pattern noise issues. But in this paper, a calibration is done (on-chip) to cancel out the FPN. And this is an interesting method : by an appropriate clocking of the reset drain, reset gate and transfer gate, the pinned photodiode is completely filled with charges to saturation, and next the pixel is readout to measure the saturation level. All this is done on-chip. The method of filling the PPD through the reset and transfer transistor is neither new (developed by TU Delft), but to use this method for the on-chip calibration is new.
The readout chain is based on column parallel 13-bit counting ADCs with digital CDS.
The stacking technology (45 nm/65 nm, TSMC) has several interesting advantages, such as the use of the MIM caps for the in-chip sample-and-holding. In this way the caps can be made larger (= lower kTC) and the presence of the caps has no influence on the fill factor. Another advantage is the quantum efficiency, reported is 95 % in green and 36 % at 940 nm. Nothing is mentioned about MTF, the high QE at 940 nm suggests that a thick epi layer is used, and that is not always beneficial for MTF.
Some more numbers : pixel size 2.7 um, 110 dB dynamic range (with HDR), PRNU is 0.6 %, full well is 10,000 electrons and the random noise is 3.5 electrons. Shutter efficiency 20,000:1.
University of Michigan presented “Energy-efficient low-noise CMOS image sensor with capacitor array-assisted charge-injection SAR ADC for motion-triggered low-power IoT applications”. Quite some time of the presentation was spent on the working principle of the ADC, apparently the ADC concept was already presented at ISSCC2016. In a few words : the large capacitor array needed in a classical SAR is replaced by a current/charge injector which is controlled by a digital switch.
Motion detection in a sensor can be done in the pixel (requires a pixel modification with reduced image quality), outside the array (requires extra memory) or in the column (called near pixel). The latter concept is used in this presentation. Only a minor extra hardware in column is added to allow the motion detection capability of the imager.
Pixel size is 1.5 um, 792 x 528 pixels, 65 nm 1P3M technology of TPSCo. Interesting to see was the power breakdown : energy/frame/pix = 63.6 pJ (ADC + pixel).
Albert, 19-02-19
For paper 1 comments “…. row-select switch to allow the pixel to run in a global shutter mode without the extra sampling in the pixel for the global shutter mode.” should the second “global shutter mode” be “rolling shutter mode”?
Good catch, you are right. Thanks for the comment, I will correct the text. Albert.