ISSCC2018 (2)

Kumagai (Sony) talked about about a 3.9 MPixel Event-Driven BSI stacked CIS.  It is not the kind of sensor that is being researched by the group of Tobi Delbruck, neither what is being done at Chronocam.  But in this new device, the data is reduced drastically by on-chip binning, column wise as well as row wise.  The overall resolution of 3.9 Mpixels is reduced to on 16×5 macro pixels.  In this “macro” pixel mode, the power consumption is drastically reduced as well, and the sensor behaves in a sort of sleeping mode.  Once the sensor detects any motion in the image (by means of frame differencing), the device wakes up and switches to the full resolution mode.  Also in the full resolution mode, the CIS works at 1.8 V supply voltage.  So that keeps the power consumption low, also in full resolution.  The device is realized in 90 nm 4CU CIS technology, on top of a 40 nm 1Al6Cu logic chip.  Pixels are 1.5 um x 1.5 um.  In full resolution, 60 fps, 10 bits, the device consumes 95 mW.  In sensing 16×5 macro pixel mode, the power is lowered to 1.1 mW at 8 bits and 10 fps.  Random noise is 1.8 e, resulting in a dynamic range of 67 dB at 10 bits and full resolution, and of 96 dB in the sensing 16 x 5 mode.


Chou (TSMC) explained the ins and outs of a 1.1 um CIS 13.5 Mpixel, 34 fps with switching options to 514 fps at 720p, 230 fps at 1080p and 58fps at 2160p.  The basic idea is to skip columns in the reduced resolution modes, while still using the full bank of column-level ADCs.  In this way 2 or 3 rows can be read out at the same time which increases the frame rate.  Because the different options to connect the columns to the ADCs, the interconnect is a bit complex, but of course the design and lay-out of the device has to be done only once.  Some numbers : technology used for the sensor is 45 nm 1P4M, for the logic 65 nm 1P5M.  Noise is 1.8 e, column FPN 0.28 e, full well 4458 e, resulting in a dynamic range of 67.5 dB.

Yasue (NHK) presented a new 8K4K device for ultra-HD broadcasting applications.  Needs to be ready to provide us with super quality slow motion pictures of Tokyo 2020 !  The sensor runs in a progressive mode.  Key characteristics are low noise (for that reason a 3-stage pipeline ADC is used), duplicated source followers with parallel operation (to speed up the device) and an ultimate speed of 480 fps (to realize the super slomo option).  The pipeline ADC consists of a folding integration stage, a cyclic stage and a SAR stage.  In 120 fps mode, the ADC works at 14 bits (noise is 3.2 e, 12.5 W), in 240 fps mode, the ADC works in 12 bits (noise is 4.3 e, 9.8 W)  and finally in the 480 fps mode, the ADC works in 10 bits (noise is 24 e, 9 W).  Apparently the specs are almost met in the 120 fps mode (target was 3 e of noise), but there seems to be room to improve at 480 fps.  Maybe next year’s ISSCC ?


Albert, 14-02-2018.

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