International Image Sensor Workshop (4)

Some thought about day 4 :

  • a student presentation from Shizuoka university about a fully-depleted SOI based detector : the conversion part is located in the base substrate, while the circuitry is located in the thin top layer silicon of the SOI.  Very clever solution for this BSI sensor, although that some parameters still have some room for improvement,
  • a stacked device from JPL with their delta-doped interface layer.  The latter gives a highly doped, ultra-thin top layer without any damage to the structure, resulting in a very stable device, even after radiation,
  • Invisage presented a paper about their quantum dot based image sensor.  Finally some numbers were shown, the devices are characterized by kTC noise and (still) a relative large dark current (600 electrons/pixel/sec at 60 deg.C for a 1.5 um pixel pitch).  A very interesting feature of these devices is the fact that they can detect electrons OR holes, depending on the polarity of the bias voltage,
  • Another quantum dot paper from imec, based on 6 nm PbS dots in a 3-layer film of a total thickness of 150 nm.  The authors showed some preliminary results, a 2D sensor is not yet realized.  Come and see at IISW2019,
  • ISAE illustrated their further work on radiation hardening of CMOS image sensors.  In conclusion : a pMOS degrades faster than an nMOS, a PPD is not suited for Grad radiation tolerance, shallow diodes can withstand radiation better than deeper diodes and a 1.8 V architecture is the best if radiation hardness is concerned.
  • Tower had a paper about different PD structures to enhance near-IR detection.  4 PD were compared : a 3 um deep diode, a 6 um deep diode, a 9 um high-resistivity and a 12 um high-resistivity substrate.  All results reported were done on a GS 2.8 um pixel.  Accutally all variations still suffer from optical cross-talk.  For that reason, in Tower’s 65 nm process, a stacked PD will be introduced : two structures on top of each other made in a double epi-layer and with an implanted isolation.
  • Canon showed an improved version of their sensor that was already introduced at IEDM 2016 and ISSCC 2017.  A lightpipe and a double micro-lens were added over previous versions.  130 nm CIS process with 1P4M + LS, 3.4 um pixel, 79 dB dynamic range, 1.8 electrons of noise and PLS of -89 dB.
  • A very similar paper came from TPSCo about double micro-lenses, but on a pixel of 2.8 um.  The presenter claimed that in the near future also light pipes will be added and that a PLS of 83.5 dB can be obtained.
  • IMEC opened the GS session with a fully depleted device with 52 um pixels and with a charge transfer of 6 ns.
  • A BSI imager with GS from ON semi, most probably with a storage node in the charge domain (a pixel architecture was not disclosed), and with a shielding of the storage node by means of implantations.
  • ams (formerly CMOSIS) closed the workshop with a large area device having GS pixels based on their in-pixel voltage storage nodes.  47 Mpixels, 30 fps, 90/65 nm, only 2 layers of metal resulting in a total optical stack of 1.5 um, DTI and stitched in 1 direction.  Angular dependency of the light sensitivity was shown as well as angular dependency of the PLS (have never seen this before at a conference or workshop).

Albert, 02-06-2017.

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