International Image Sensor Workshop (3)

Some thoughts about day 3 :

  • Several ADC papers were presented, with a common motivation : hybrid ADC solution for the image sensor application : Tokyo Institute of Technology highlighted a SAR in combination with a delta-sigma ADC (without indicating the number of bits in their paper), University of Oxford combined a single-slope with a TDC solution to realize a fast 12-bit ADC, Teledyne DALSA presented a fast SS-ADC used in their TDI-CCD/CMOS combination, Teledyne Anafocus came up with a column-parallel solution based on two-stage oversampled converters, and finally Olympus presented a SS-ADC with a operation-period-reduced TDC to increase the conversion speed and keep the power consumption low.
  • In between all those ADC papers, Delft University showed an on-chip digital calibration technique to correct the non-linearity of the pixels.  Actually this calibration technique is based on “shaping” the ramp of the SS-ADC, so also this paper was referring to ADC related stuff.
  • In the final session of day 3 a collection of papers was presented on various topics.  JPL gave an overview and update of their latest image sensor work, university of Toronto talked about a CMOS architecture fo a so-called primal-dual coding with on-chip programmable masking techniques for the pixels (pixels are based on a good-old photogate), Sony re-presented their ISSCC paper on a stacked device with a very powerful 140 GOPS column parallel processing capability, and the session was closed by IMEC reporting a high-speed BSI version of their TDI CCD-CMOS combination.  Quite a bit of CTI-, noise-, MTF- and dark-current measurement data was shown in this last presentation with the comment of the speaker that there is still room to improve considering the performance of the device.

Albert, 01-06-2017.

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