ISSCC2015 (2)

A second paper in the imaging session highlighted the work of NHK in cooperation with Forza Silicon.  A 133 Mpixel (yes, you read it right, one hundred thirty three), 60fps device was described.  The device has on-chip ADC’s, 1 SAR 12-bit ADC for 32 columns.  The ADCs are located at both sides of the device, 242 ADCs at the top and 242 ADCs at the bottom of the chip.  Each SAR ADC has 14 redundant bits, but at the output each pixel is represented with 12 bits.  The pixel size is 2.45 um, 2×1 shared, 2.5T/pixel, 35 full-frame format.  Fabrication was done in 0.18 um 1P4M technology.  Due to its large size, the chip is stitched in one direction.  [There are not that many foundries that allow stitching in a CIS 0.18 um process, so it is easy to guess who fabricated this device.]  At full speed, the device is delivering 1.15Gbps/ch, maybe that does not sounds that much, but the device has 112 channels in parallel.  So in total, this adds up to almost 130 Gbps.

To capture all the information and to get all these bits off the chip, a total power consumption of 11 W is needed.  About 50 % of this power goes to the digital blocks.  All ADCs take 1.67 W.  A few more numbers : conversion gain of 80 uV/e, full well 10005 electrons (don’t forget the last 5 electrons), dark current 50 e/sec @ 40 deg. C, temporal noise 7.68 electrons and dynamic range of 62.3 dB (data measured at 60 fps, gain of 2).

Albert, 26-02-2015.

Leave a Reply