ISSCC2015 (1)

The imaging session at this year’s ISSCC started with a presentation of A. Suzuki of Sony.  He presented a 20 Mpixel, stacked image sensor for DSC applications.  The stacked device has on the top plane the imaging part, being 2×2 shared pixels of 1.43 um pitch.  Also included on the top layer of silicon are the column electronics.  The end/output of the column circuits are connected to the second layer of silicon by vias.  This is the same concept as presented on last year’s ISSCC.  Half of the column signals is transferred to the second silicon level at the top of the sensor, the other half of the column signals is transferred to the second silicon level at the bottom of the sensor.  The author did not reveal information about via pitch.

New is the DOUBLE single-slope ADC for every column, located on the second layer of silicon.  So every pixel can be converted into the digital domain twice and in parallel, resulting in a double sampling of the data.  If the timing of the ADCs is done right, a gain of 3 dB can be realized (= to the theoretical calculation).  In this configuration of multiple sampling, the resulting noise level is 1.3 electrons for a gain of 27 dB.  But the double column-ADC can also be used in other configurations.  For instance for high-speed applications.  Instead of feeding to the two ADCs the same signal, one can also offer two different signals to the ADCs and in this way increasing the overall speed of the sensor.  This feature can be attractive for slow-motion applications.  Numbers quoted : 120 fps at 16 Mpix resolution (10 bits with on-chip data compression), 240 fps at 4 Mpix resolution (10 bits) and 960 fps at 0.7 Mpix resolution (10 bits).  For still applications, one can use the sensor with 20 Mpix resolution, 12 btis and a frame rate of 30 fps.

The final application of the dual ADC for each column is a combined of video and still capture.  While shooting the video at higher frame rates using the first ADC for each column, one can grab a single still image at full resolution using the second ADC for each column.

Some more numbers : sensor technology 90 nm 1P4M BSI, logic technology 65 nm 1P7M with 1.7 Mlogic gates on the second silicon level.  Number of pixels 5256 (H) x 3934 (V), 1/1.7 inch, full well 9700 electrons, conversion gain 76.6 uV/e, dynamic range 72 dB at 12 bits.

Albert, 24/2/2015.

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