Next are two (short = 15 min) presentations of imagers with a 3D-fabrication technology. The first paper was coming from Olympus, entitled “A rolling-shutter distortion-free 3D stacked image sensor with -160 dB parasitic light sensitivity in-pixel storage node”, by J. Aoki. The device is made out of a double layer structure : the top layer holds the BSI photodiode array, the bottom layer has the storage as well as the column processing present. The architecture of the pixels is a 4-shared BSI-PPD pixel structures with all 4 photodiodes, four transfer transistors, one floating diffusion one reset transistor and one source follower in the top layer. Next a bump is connecting the source follower from the top layer to the bottom layer. In the latter the select transistor is present plus 4 sample-and-hold switches and capacitors. These are acting as the storage nodes to construct the global shutter. Next these storage nodes are provided with an individual source follower and select transistor. So for every group of 4 pixels, one micro-bump is needed to provide the electrical contact. Between the two layer an opaque shield is inserted to shield the storage nodes from any incoming light. That is the explanation of the -160 dB light shielding efficiency.
Very simple, but apparently very efficient solution. Nevertheless only very limited performance data was shown. Pixel size is 4.3 um x 4.3 um, 30 frames/s, minimum bump pitch 8.6 um, 704 x 512 pixels and fabricated in 0.18 um 1P6M process. Unfortunately no data about noise or dark current. Remarkable is the mentioned full well capacity : 30,000 HOLES. Although no further comments were given (neither asked) : this is a hole detector with all circuitry based on p-MOS transistors.
Next on in line was the Sony presentation by S. Sukegawa : “A 1/4-inch 8M pixel back-illuminated stacked CMOS image sensor”. The basic idea is to use the carrier substrate of the BSI structure as an active layer and put all the circuitry onto/into this carrier layer. Very simple, straight forward but a challenging technology ! In the device presented, the connection between the two layers is made by TSVs. These TSVs are located at the outside of the die, so no connections or TSVs in the active area. Unfortunately no pictures or cross-sections, neither any data was given about the TSVs.
As far as circuitry on the top layer is concerned, the following is included : full imaging array, addressing means as well as the comparators in the column circuitry which are front-end part of the column-level ADC. The counters, being the back-end part of the column-level ADCs are located in the second layer. This architecture suggests that every column has a TSV, or that a limited number of TSVs is used in combination with a multiplexer and de-multiplexer. But no information was given about this.
The top part was fabricated in a 90 nm CIS process, the bottom part in a 65 nm logic process, containing 2.4 Mgates. The overall chip size is 70 % of the one that was made in one single layer.
As far as the CFA is concerned : RGBW arrangement is used, firstly reshaped in a Bayer pattern and next demosaiced. The device also has the option to alternately have lines with long and lines with short exposure time to extend the dynamic range. So overall it is not surprising that that many logic gates are used in the bottom layer, it contains a lot of image processing stuff. Some key performance parameters : 5000 electrons full well for a pixel of 1.12 um x 1.12 um, 30 fps in full resolution, 2.2 electrons of noise with an analog gain of 18 dB and a conversion gain of 63.2 uV/electron.