Harvest Imaging Forum


Go to the Forum Introduction page


Go to the Forum Registration page

Agenda of the forum "Low-Noise Analog CMOS Circuit Design : from devices to circuits"

Noise represents the ultimate limitation of signal resolution for analog circuits. The design of low-noise analog circuits therefore requires a good understanding of the fundamental noise sources in electronic devices and the propagation mechanisms in circuits. In addition to shot and thermal noise, the noise at low frequency is often dominated by 1/f noise in advanced CMOS technologies. The latter can be eliminated thanks to various offset and noise reduction techniques including autozero, correlated-double-sampling (CDS), correlated-multiple-sampling (CMS) or chopper stabilization. For low-noise analog circuit design, it is therefore crucial to understand the features and differences between these different techniques in order to select the most appropriate for the targeted application. This is particularly true for the design of low-noise imagers, which include all of the above aspects.

This lecture starts with the presentation of the mathematical tools needed for analyzing and optimizing noise in circuits. The definition of power spectral density and its use for the calculation of noise bandwidth and noise power are given. The different types of noise, their origin and properties are described, including thermal, shot and flicker noise. The noise models of passive and active devices are then described with a special focus on the photodiode and the MOS transistor. After having described noise in components, we then look into how noise propagates from the various noise sources to the output and show how to calculate the total noise at the output of continuous-time circuits. The analysis allows identifying which are the fundamental device and circuit noise parameters and how they can be optimized for low-noise. The concept of inversion coefficient IC as an essential design parameter is then presented. Several figures-of-merit (FoM) including the current efficiency Gm/ID , the transit frequency Ft and their product (Gm∙Ft)⁄ID , capturing the various trade-offs encountered in analog circuit design are presented. The trade-off between noise and power consumption in terms of IC is then illustrated by several elementary single transistor circuits, including the source follower stage, which plays a crucial role in the pixels of CMOS imagers. The effect of noise sampling and aliasing occurring in sampled-data circuits such as switched-capacitor (SC) circuits is then described. A simple technique for calculating noise power in SC circuits is presented. The basic principles for low frequency noise reduction techniques are then discussed namely autozero and correlated-double and -multiple sampling for sampled-data circuits and chopper stabilization for continuous-time circuits. The effect on 1/f noise and broadband noise for each of these techniques are clearly highlighted. The lecture ends with the presentation of the analysis and optimization of a complete CMOS 4 transistors pixel and the associated read-out chain. Based on this analysis, some future trends for implementing low-noise imagers in advanced CMOS processes are drawn.

Forum Agenda

  1. Introduction

  2. Random signals and noise

    • Random or stochastic process

    • Power spectral density

    • Noise in linear systems

    • Noise types

    • Equivalent noise bandwidth

    • Summary

  3. Main noise sources in electronics components

    • Thermal noise

    • Shot noise

    • Flicker Noise

    • Summary

  4. Noise of basic components

    • Resistor

    • Diode, Photodiode

    • MOS transistor

    • OP-AMP

    • Summary

  5. Noise calculation in continuous-time (CT) circuits

    • Basic principle

    • Example: simple OTA

  6. Trade-offs between noise and power consumption

    • The concept of inversion coefficient

    • Specific current extractor and ratio-based design technique

    • Basic trade-offs in analog and RF design

      • The minimum supply voltage trade-off

      • The power-speed trade-off

    • Figures-of-merit (FoMs) as design guidelines

      • The current-efficiency G_m⁄I_D FoM

      • The transit frequency F_t FoM

      • The (G_m∙F_t)⁄I_D FoM

    • Difference between designing using a FoM and optimization

    • Noise-power trade-off in basic single transistor circuits

      • Common-source

      • Source follower

      • Common gate

    • Summary

  7. Noise calculation in switched-capacitor (SC) circuits

    • Sampled noise

    • Noise mechanisms in SC circuits

    • Noise calculation methodology

    • Examples

      • Integrators

      • Basic gain stages

      • Track-and-hold stage

      • 1st-order low-pass filter

    • Noise simulation of SC circuits

      • Transient noise simulation

    • Summary

  8. Noise and offset reduction techniques

    • Switch non-idealities

    • Autozero (AZ)

    • Correlated Double Sampling (CDS)

    • Correlated Multiple Sampling (MCS)

    • Chopper Stabilization (CS)

    • Summary

  9. Example of a low-noise CMOS imager

  10. Future trends