TDI presentations at 2015 CMOS Workshop CNES (Toulouse, Fr).

Time-Delayed Integration or TDI in CMOS seems to be a hot topic (at least for space applications), but it also still is a challenging architecture to build in CMOS technology.  At the CNES CMOS image sensor workshop in Toulouse (held about 10 days ago), there were several presentations on CMOS-TDI, here is an overview.

C. Virmentois presented the CNES work on TDI.  They finished several projects with ESPROS (CCD on CMOS), IMEC (CCD on CMOS) and ST (digital CMOS TDI).  At this moment work is going on in the field of a multi-spectral TDI with large pixels, also this latest device is based on a digital TDI.

W.r.t. to the chip(s) made at ESPROS, the following details were given :

  • Fully depleted, BSI,
  • 7.5 um and 6.5 um pixel pitch for monochrome,
  • 26 um and 52 um pixel pitch for multi-spectral,
  • noise level of 600 uV,
  • dark current of 2.6 nA/cm2 at 20 oC,
  • conversion gain : 10… 15 uV/e,
  • CTI : 2.10-3,
  • INL < 1.5 %,
  • FWC : 92 ke at 1 V,
  • QE > 70 % n-IR.

A second chip made at ESPROS showed improved results, such as :

  • Noise : 350 uV,
  • Dark current : 1ke/s (= 10 x less),
  • CTI : … 1.10-4

During the presentation it was not mentioned which part of the processing was done by ESPROS and/or which part of the processing was done by a third party.


M.-Y. Yeh of NAR Labs reported the work on TDI done in his lab :

  • 6 lines, 2 PAN + 4 multi-spectrum,
  • 7.5 um pixel pitch for PAN and 30 um pixel pitch for multi-spectrum,
  • Based on 4T BSI 2.5 um pixels, made in TSMC 0.11 um process,
  • Stitched with 8 blocks next to each other, chip width : 12.288 cm.


F. Mayer of e2v mentioned that the first TDI made by his company was already done in 2010 with charge transfer in a 0.18 um CMOS process.  Later more CCD-like devices were made.

For the digital domain, Frederic mentions :

  • Too much load for the ADC,
  • Motion MTF issues,
  • Dynamic range is OK, but the noise is pretty high.

For the charge domain :

  • Limitation in full-well capacity.

The combination of digital and charge domain can overcome a number of drawbacks, but the architecture will be pretty complex.

The first generation charge transfer TDI was built on a surface channel CCD, the second generation was provided with a buried channel.

Neither in this presentation the fab was mentioned that fabricated the CMOS wafers.


Ben-Ari of SemiConductors Devices gave a large list of performance data of the TDI’s made by his company.

In summary :

  • 4 independent TDI arrays,
  • digital running TDI with global shutter,
  • 0.18 um technology,
  • Chip size : 84 x 16 mm2, 2600 pixels x 8 to 64 pixels,
  • Full well : 300 ke, < 80 e noise, and 72 dB dynamic range,
  • 50 … 10,000 lines/s,
  • Dark current < 400 e/s at 25 oC,
  • Single slope ADC,
  • Stitched in 1 dimension,

Current status of these devices : BSI delivered, wafer sort done with good yield.


Boulenc gave an overview of IMEC’s TDI status :

  • 0.13 um, CMOS flow with 3.3 V and 1.5 V power supply,
  • Generation 1 (see also CNES presentation) with lateral AB and dedicated implants at the output to make it BSI compatible,
  • Generation 2 : 5 um pixel size, 1025 x 512 pixels, gate spacing between 100 nm and 180 nm, CF : 25 uV/e, 2.5 nA/cm2 dark current at 25 oC, 0.5 mV noise floor and 17 ke full well capacity,
  • Generation 3 is in development.


In conclusion : a lot of interesting work is going on in the field of TDI-CMOS, but apparently none of the developments has yet resulted in commercially available devices with a performance that matches the existing TDI-CCD performance.  It is more difficult than expected to beat the TDI-CCD noise-free charge transfer in sub-pixel steps in combination with a low dark current.  Depending on which side of the table you are sitting, this can be bad news (for the customers eagerly waiting for TDI-CMOS) or this can be good news (for the engineers, because there are still enough challenging developments ahead of us).

Albert, 26-11-2015.

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