Some thoughts about day 2 :
- two back-to-back papers of Dartmouth about the QIS. The first paper described basically the work on a single Jot with reset-gate less pixel, with a tapered reset gate, with a JFET readout and with a buried channel readout, all fabricated in a stacked 45nm/65 nm BSI TSMC technology. Some numbers : 1.1 um pixel pitch, 540 uV/electron conversion gain, best noise as low as 0.22 electrons. The second paper talked about the integration of the Jots in an array. The testdevice has 1 Mpixel. The promise made : by 2019 they will show 100 Mpixel.
- the largest SPAD array ever was reported by EPFL, while the smallest SPADs came from University of Edinburgh.
- also the university of Edinburgh reported about the transformation of QIS bitplanes to compensate motion. The paper was supported by spectucular images,
- Delft University presented a SPAD integrated on a flexible substrate with the capability of being sensitive from both sides of the device,
- a dedicated ToF session opened with a paper from Shizuoka University illustrating a 3-tap ToF sensor (normally 2-tap or 4-tap devices are shown), also 3-taps in a paper of the University of Lyon in cooperation with ST and CEA-Leti. The latter was made on a “doping-profile-controlled” epi-layer to enhance the transport of the electrons to the collection nodes,
- several years ago Samsung presented material on RGB-Z sensors, also at the workshop they showed an alternative concept for a RGB-Z device based on structured light with a green laser beam. The device included a simple trick to cope with a large amount of background light : using the FD-RST combination as a logarithmic pixel.
- HDR was, is and remains a hot topic. Apparently everyone is seeking a solution that does not suffer from motion artefacts. This can be done by “playing” around with the gain of the output structure by adding an extra capacitor. This idea can be found in the work of Brillnics (3 different conversion gains, 87 dB, 3.0 um pixel), ON Semi (extra in-pixel capacitor like LOFIC, 98 dB, 6 um pixel pitch), Caeleste (extra in-pixel capacitor in combination with extra gain in the columns, 92 dB, 12 um), ON semi (multiple reads of the PPD with storage on an external capacitor, 140 dB, 3 um pixel pitch), OmniVision (extra in-pixel capacitor, 120 dB, 2.8 um pixel pitch). Apparently once the sensor does better than 120 dB, the sensor is no longer the limiting factor as far as DR is concerned,
- “out-of-the-box” is the solution proposed by ST : detection, collection and readout of electrons as well as holes. The electrons are collected in the classical way (FWCe = 33000), the holes are stored in the capacitances of the DTIs which has a very large total storage capacitance (FWCh = 750,000). Result : 116 dB dynamic range in a 3.2 um pixel pitch,
- between all the HDR stuff, Delft University presented a 0.5 electron noise device with correlated double sampling in the charge domain. A conversion gain of over 1.5 mV/electron was reported measured on a device made in a standard 0.18 um CIS process,
- Ritsumeikan University calculated the temporal resolution limit of silicon imagers. The result is around 11 ps. So still a long way to go before we reach the maximum frame rate corresponding to this limit, being 90 Gfps,
- high-speed devices were presented by Tohoku University (based on burst mode with analog memories outside the active imaging area, 10 Mfps, 960 frames), Vrije Universiteit Brussel (burst mode based on in-pixel storage, 20 Mfps, 108 frames), Tokyo University ( 0.64 usec row-time), and AGH University of Krakow (70 kfps for a device with 75 um pixel pitch intended for XRD applications).
Sorry for any typos or for any missing papers, also day 2 had again a lot of information : 2 invited papers and 23 submitted papers !
Albert, 31-05-2017.