The fight on stacking has began. After Sony’s presentation at ISSCC, others are following on the stacked road. Omnivision shows their architecture on stacking with the TSV’s outside the imaging array. They claim to have the technology ready to start production of stacked imagers with a pixel pitch of 1 um. Olympus showed their improved work over the one presented two years ago at ISSCC. Olympus has a contact between the two silicon layers for every group of 2×2 pixels. They created a 16M pixel device with 4M direct contacts, each with 7.6 um pitch. Extra added to the ISSCC paper is the CDS capability buried in the second layer of silicon. Also remarkable : all circuitry on the top level silicon is p-type ! Because a metal light shield is used between the two layers of silicon, a PLS of -180 dB is obtained. Giant steps forward in their stacked wafer-to-wafer imager process.
Like Olympys, also NHK showed a wafer-to-wafer bonding using Au contacts. Nice to get also some information about the technology of the bonding itself. TSMC had a paper about the photon emission in a stacked CIS. Of course the second layer with the processing circuitry in a stacked image sensor is not designed/optimized for imaging purposes, and consequently during operation the circuitry present in this layer can generate some light that can be captured by the top layer. This is no longer PLS but SLP, because the light is coming in the opposite direction. Also the last paper in this session came from TSMC and dealt with dark FPN improvement by a stacked CIS process. Focus was put on the decomposition of the FPN by biasing/switching the TG in an appropriate way.