Archive for June, 2015

International Image Sensor Workshop 2015 : Stacked Imagers

Tuesday, June 23rd, 2015

The fight on stacking has began.  After Sony’s presentation at ISSCC, others are following on the stacked road.  Omnivision shows their architecture on stacking with the TSV’s outside the imaging array.  They claim to have the technology ready to start production of stacked imagers with a pixel pitch of 1 um.  Olympus showed their improved work over the one presented two years ago at ISSCC.  Olympus has a contact between the two silicon layers for every group of 2×2 pixels.  They created a 16M pixel device with 4M direct contacts, each with 7.6 um pitch.  Extra added to the ISSCC paper is the CDS capability buried in the second layer of silicon.  Also remarkable : all circuitry on the top level silicon is p-type !  Because a metal light shield is used between the two layers of silicon, a PLS of -180 dB is obtained.  Giant steps forward in their stacked wafer-to-wafer imager process.

Like Olympys, also  NHK showed a wafer-to-wafer bonding using Au contacts.  Nice to get also some information about the technology of the bonding itself.  TSMC had a paper about the photon emission in a stacked CIS.  Of course the second layer with the processing circuitry in a stacked image sensor is not designed/optimized for imaging purposes, and consequently during operation the circuitry present in this layer can generate some light that can be captured by the top layer.  This is no longer PLS but SLP, because the light is coming in the opposite direction.  Also the last paper in this session came from TSMC and dealt with dark FPN improvement by a stacked CIS process.  Focus was put on the decomposition of the FPN by biasing/switching the TG in an appropriate way.

Albert, 23-06-2015.

International Image Sensor Workshop 2015 : Image Sensors for Digital Photography

Monday, June 22nd, 2015

The first session of IISW2015 was devoted to larger devices intended for digital still photogrpahy.  Samsung presented a 28M APS-C sensor with BSI technology.  It is not common to go after BSI for these large dies, but apparently time and yield is ready to apply BSI to these larger devices as well.  Remarkable dark performance : 9 electrons/s dark current at 60 deg.C, 1.8 electron of random noise at 24 dB gain.  The architecture is charactereized by 1 ADC for 2 columns, double column busses and an optimized read sequence to allow for binning.

Canon described their sensor with phase-detection auto-focus pixels in EVERY pixel.  This solution allows for no light shield in the auto-focus pixels and no interpolation of the auto-focus pixels.  This sensor is already avaialable in Canon cameras, but it is the first time Canon publishes technical information about the device.  Because of the dual photodiode in every pixel, every pixel is provided with two readout structures, so every pixel has 8 transistors.  Random noise level of 1.8 electrons is reported at gain = 32 for a single photodiode.

Also Sony presented a CMOS imager with auto-focus functionality in every pixel.  This sensor is provided with a diagonal pixel orientation, so that the rows have alternatively G pixels and R/B pixels.  To make this sensor compatible with the installed software base, first of all the pixel stream is converted into Bayer RGB.  Also of interest for this sensor architecture with a dual PD in every pixel is the option for HDR by using 1 PD/pixel for a short exposure and 1 PD/pixel for a long exposure time.

Teledyne DALSA published one of the very few CCD papers at the workshop, mainly large area devices, e.g. 32M, 60M and 250M.  Remarkable is the ultra low dark current for these devices : 2 pA/cm2 at 60 deg.C.  These low values make these devices very well suited for extremely large expsoure times.


Albert, 22 juni 2015.

International Image Sensor Workshop 2015 : General Trends

Friday, June 19th, 2015

Some interesting trends in image sensor technology for consumer applications are :

– the incorporation of deep trench isolation (DTI) between the pixels to lower the optical and electrical cross talk.  Announced were already DTI defined from the front side (ST) as well as the back side (Samsung), but new at the workshop are the DTIs that do not completely go through the thinned BSI silicon,

– building “walls” between the colour filters (called “buried CFA”) is finding its way to production.  These walls limit optical and spectral cross-talk,

– very thin optical stacks, down to 1.5 um for BSI sensors,

– incoroporation of focus pixels for auto-focusing purposes.  These focus pixels can be incorporated in a regular pattern, but sometimes a semi-random pattern is used as well.  Moreover, the focus pixels do not need to be all of the same size,

– stacked imager are more and more introduced.  During IISW 2009, the buss word was BSI, now it is “stacked”.  Stacked imagers are going to solve all the problems ….

– the incorporation of W pixels continues, in more recent devices, up to 50 % of the pixels are W pixels.

In conclusion : no major new technologies were introduced, neither any pixel size below 1 um, but everything is getting better in performance and more compact in size.

Albert, 19/06/2015.


Saturday, June 13th, 2015

As already announced earlier, also in 2015 there will be a Harvest Imaging Forum.  All forum information is now on-line, including agenda and registration form.  More info can be found at

Albert, 13-06-2015.