Archive for February, 2015

ISSCC2015 (4)

Friday, February 27th, 2015

Also this year Shizuoka University was present at the ISSCC with an imager paper.  Mochizuki presented a single-shot 200 Mfps 5×3 Aperture Compressive CMOS Imager.  The chip consists of 5 x 3 subarrays (multi-aperture), and each subarray has 64 x 108 pixels, each of 11.2 um x 5.6 um.  The chip is fabricated in 0.11 um CIS technology.  The 15 sub-arrays all receive the same image information, each sub-array has its own micro-lens.  But the difference between the 15 sub-arrays is the exposure time.  For each sub-array the exposure time is modulated/changed/scrambled in the time domain, such that all the different sub-arrays grab parts of the secenery but all in different and sometimes mixed time slots.  In this way, the information readout is a kind of compressed information in the time domain.  After solving/reconstructing, the 15 images shot at the same time (= NOT the same exposure time !) result in 32 different frames in the time domain.  Thus the sensor has an inherent compression of 47 %.

As many other papers of Shizuoka University, also this paper is relying on a clever pixel design around a PPD, with a lot of knowledge in the device physiscs field.  The paper described very nicely the principle of the compressed sensing, including simulation as well as measurement results.

Albert, 27-02-2015.

ISSCC2015 (3)

Thursday, February 26th, 2015

Here is another one : a paper of Samsung, presented by dr. Choi.  His paper can be seen as a kind of continuation of his work he did for his PhD at Univ. of Michigan : having a sensor ALWAYS TURNED ON in a kind of hibernation mode (= ultra-low power, low resolution, low quality), but waking up as soon as there is any movement in the scene and switching to a normal mode (= higher resolution, higher quality).  Classical ways to lower power is reducing speed, reducing resolution, reducing number of bits, etc.  But what I appreciated very much in this work were two additional techniques to lower the power :

– using a classical PPD pixel in the normal mode at 3.3 V, and using the same pixel (with TG always switched ON) in a kind of 3T pixel mode operating at 0.9 V (with reduced performance),

– turning the circuitry of two adjacent PGA’s (of 2 adjacent columns in the normal mode) into an 8-bit SAR ADC for the low-power, low quality mode.

In this way the power of the ALWAYS ON mode was reduced by a factor of 500 compared to the normal mode.  Final power consumption was 45.5 uW.

Some more numbers (Numbers add up to Nothing ! Neil Young in “Powderfinger”) : reduced resolution (/4), same fps (30 fps), supply voltage reduced from 3.3 V analog/1.8 V digital to 0.9 V for all, sensitivity down by a factor of 4, FPN went up 20 x (but still less than 1 %)and random noise went up by 4x (expressed in DN, but is 1 DN in the high-quality mode equal to 1 DN in the low-quality mode ???).  But power goes down by 500 times !

Albert, 26-02-2015.

ISSCC2015 (2)

Thursday, February 26th, 2015

A second paper in the imaging session highlighted the work of NHK in cooperation with Forza Silicon.  A 133 Mpixel (yes, you read it right, one hundred thirty three), 60fps device was described.  The device has on-chip ADC’s, 1 SAR 12-bit ADC for 32 columns.  The ADCs are located at both sides of the device, 242 ADCs at the top and 242 ADCs at the bottom of the chip.  Each SAR ADC has 14 redundant bits, but at the output each pixel is represented with 12 bits.  The pixel size is 2.45 um, 2×1 shared, 2.5T/pixel, 35 full-frame format.  Fabrication was done in 0.18 um 1P4M technology.  Due to its large size, the chip is stitched in one direction.  [There are not that many foundries that allow stitching in a CIS 0.18 um process, so it is easy to guess who fabricated this device.]  At full speed, the device is delivering 1.15Gbps/ch, maybe that does not sounds that much, but the device has 112 channels in parallel.  So in total, this adds up to almost 130 Gbps.

To capture all the information and to get all these bits off the chip, a total power consumption of 11 W is needed.  About 50 % of this power goes to the digital blocks.  All ADCs take 1.67 W.  A few more numbers : conversion gain of 80 uV/e, full well 10005 electrons (don’t forget the last 5 electrons), dark current 50 e/sec @ 40 deg. C, temporal noise 7.68 electrons and dynamic range of 62.3 dB (data measured at 60 fps, gain of 2).

Albert, 26-02-2015.

ISSCC2015 (1)

Tuesday, February 24th, 2015

The imaging session at this year’s ISSCC started with a presentation of A. Suzuki of Sony.  He presented a 20 Mpixel, stacked image sensor for DSC applications.  The stacked device has on the top plane the imaging part, being 2×2 shared pixels of 1.43 um pitch.  Also included on the top layer of silicon are the column electronics.  The end/output of the column circuits are connected to the second layer of silicon by vias.  This is the same concept as presented on last year’s ISSCC.  Half of the column signals is transferred to the second silicon level at the top of the sensor, the other half of the column signals is transferred to the second silicon level at the bottom of the sensor.  The author did not reveal information about via pitch.

New is the DOUBLE single-slope ADC for every column, located on the second layer of silicon.  So every pixel can be converted into the digital domain twice and in parallel, resulting in a double sampling of the data.  If the timing of the ADCs is done right, a gain of 3 dB can be realized (= to the theoretical calculation).  In this configuration of multiple sampling, the resulting noise level is 1.3 electrons for a gain of 27 dB.  But the double column-ADC can also be used in other configurations.  For instance for high-speed applications.  Instead of feeding to the two ADCs the same signal, one can also offer two different signals to the ADCs and in this way increasing the overall speed of the sensor.  This feature can be attractive for slow-motion applications.  Numbers quoted : 120 fps at 16 Mpix resolution (10 bits with on-chip data compression), 240 fps at 4 Mpix resolution (10 bits) and 960 fps at 0.7 Mpix resolution (10 bits).  For still applications, one can use the sensor with 20 Mpix resolution, 12 btis and a frame rate of 30 fps.

The final application of the dual ADC for each column is a combined of video and still capture.  While shooting the video at higher frame rates using the first ADC for each column, one can grab a single still image at full resolution using the second ADC for each column.

Some more numbers : sensor technology 90 nm 1P4M BSI, logic technology 65 nm 1P7M with 1.7 Mlogic gates on the second silicon level.  Number of pixels 5256 (H) x 3934 (V), 1/1.7 inch, full well 9700 electrons, conversion gain 76.6 uV/e, dynamic range 72 dB at 12 bits.

Albert, 24/2/2015.