Albert Wang (Cornell University) reported about “An Angle Sensitive CMOS imager for single-sensor 3D photography”. Very interesting new technology in the 3D world. An image sensor is described that is capable of detecting the direction of the incoming rays, and based on that, the object distance can be calculated. In other words, a depth map can be created. The main application for this sensor are ranging and computational refocus.
The sensor itself is based on a regular CMOS device overlaid with two grids (made in M3 and M5). A kind of interference effect is generated by means of these two grids depending on the angle of the incoming rays. The overall working principle is based on the so-called Talbot effect, published (and referenced !!) in 1836. [Talbot is also the bass player of Crazy Horse, the band of Neil Young. It remains a small world]
To become a commercial product, still a long way needs to be travelled I guess, but it is a very appealing concept because it does not need any extra laser pulse, and makes use of the direct incoming information through standard lenses. Something to watch.
Also a nice concept is the next paper by Robert Johansson (Aptina) : “A 1/13-inch 30fps VGA SoC CMOS image sensor with shared reset and transfer gate pixel control”. The basic question is : how to further optimize the fillfactor of a front-side illumination 4T pixel ? After putting them into a 2 x 1 shared concept, the number of metal lines going into the pixel is further reduced to 1 vertical line (column bus sharing the supply line) and 1 horizontal line (reset of line n+1 is shared with the transfer gate of line n). The sharing makes the timing a bit more complex, but that is just a matter of developing once and you’re done.
To further reduce the overall chip size, the black reference columns and lines are replaced by a small 2D area (48 x 17 pixels) to generate a black reference. Some of these pixels have the transfer gate active, others do not. This allows to get a fairly good idea about the dark current generation. Some performance numbers : CF = 272 uV/electron, read noise at maximum gain = 1.68 electron, pixel capacity at max linear range = 3400 electrons. These numbers hold for a pixel of 1.75 um pitch and a fabrication technology of 0.11 um. Total power consumption is 55 mW (but frame rate is not mentioned).
“A 1/2.33-inch 14.6M 1.4 um pixel backside illuminated CMOS imager sensor with floating diffusion boosting ” by Sangjoo Lee (Samsung) support the continuous effort in back-side illuminated devices. Thanks to the BSI, more circuitry can be afforded on the front-side, and for that reason extra FD boosting circuitry was included. This gave an extra boost of 0.67 V on the FD at a boosting pulse of 4 V (? not sure if this is correct). It was mentioned during the talk that the crosstalk of the BSI was equal to the FSI situation, but no numbers were mentioned. A nice cross section of the silicon was shown, clearly indicated a very low optical stack at the backside, and no metal grid at the backside. The noise level was down to 1.4 electron (speed ?), a full well of 5700 electrons and the SNR10 improved from 135 lux for the FSI to 87 lux for the BSI.
Very nice work and another one who is ready to join the BSI club.
“An APS-C format 14b digital CMOS image sensor with a dynamic response pixel” by Dan Pates (Aptina). To start with, the dynamic response pixel refers to a dual conversion gain in the pixel by the possibility to add an extra capacitor to the floating diffusion or not. The pixels of this sensor are pretty large (4.78 um) and thus more freedom and space is available to play around with the design. The presenter showed three different ring gate structures that avoided STI in the pixel area for isolation. These ring structures look very similar to radiation tolerant pixel designs, and also in this case the main reason to avoid STI is to reduce the dark or leakage current. In the reported numbers this low dark current (17 electrons at 60 deg.C) was shown, as well as a lower noise level (16 electrons at low gain 1x, 2.2 electrons at high gain 8x), a large fill factor, high sensitivity (49.5 kelectrons/lux.s) and large full well (50 kelectrons at low gain and 16 kelectrons at high gain).
The ADC implemented is based on SA, and contains 14 bits. Overall frame rate is 10.48 fps.
The last paper in the imaging session of ISSCC2011 was “A 17.7 Mpixel 120 fps CMOS image sensor with 34.8 Gb/s readout” by Takayuki Toyama (Sony). The sensor reported was on based on the “classical” Sony concept of column parallel ADCs based on up-down counters. But because of the extremely high bitrate of the overall chip, the 14 counters in the column are split into two parts :
– The lower 5 bit counters, which are driven with 248 columns in parallel, in such a way that the columns do not contain the real counters, but contain memory cells,
– The upper 9 bit counters, which are based on real counters as before.
This hybrid construction allows to maintain the high accuracy of 14 bits with the extremely high speed of 34.8 Gb/s overall. The device runs at 120 fps at 12 bits and 60 fps at 14 bits. The chip is realized in 90 nm technology, 1P4M and consumes a total power of 3W at 120 fps.
Overall conclusion of this imaging session : the technical committee put a great set of papers together. Not just the content of the papers were high level, so was the presentation of the papers. Congratulations to all authors, I really enjoyed a great Wednesday morning !